Analog Engineer

Intel Corporation; Hillsboro (OR); Hybrid; USD 142,000 - 269,000; Full time

Benefits offered by this job

Stock bonuses

Health benefits

Retirement plan

Paid vacation

Job summary

Intel Corporation in Hillsboro, Oregon, is seeking an experienced Analog Circuit Design Engineer to join the AD-FIP within the DTP. You will design and optimize analog/mixed-signal circuits for advanced nodes, contributing to foundational IP for client/server networks.

You will work with cross-functional teams on tape-out readiness, verify layouts, and improve performance, power, area, and yield while pushing semiconductor technology boundaries.

Qualifications

• Bachelor's degree in Electrical/Computer Engineering with 4+ years analog/mixed-signal design
• Experience with ADCs/DACs, PLLs, and high-speed interfaces is desirable
• Familiarity with tape-out flows and analog layout verification for SoC

Responsibilities

• Design, develop, and implement analog/mixed-signal circuits and IPs, including ADCs, DACs, and voltage regulators.
• Perform circuit-level design, simulation, and optimization to meet PPA targets.
• Create floorplans, extract parameters, and validate analog models for robust behavior.
• Develop test plans and verify designs to meet specifications.
• Collaborate with architecture/layout teams to maximize functionality and reliability.
• Lead tape-out activities and resolve post-silicon issues.
• Interface with process technology and product teams to influence future nodes.

Skills

Analog circuit design

Circuit simulation

CMOS technology & analog layout

Tape-out experience

SoC analog layout checks

Education

Bachelor's degree in Electrical/Computer Engineering

Advanced degree (MS/PhD) preferred

Job description

Job Details: Job Description: The Role and Impact Join Intel's Advanced Design Foundational IP Organization (AD-FIP) within the Design Technology Platform (DTP), a team that is pivotal in shaping the future of analog and mixed-signal IC design. As an Analog Circuit Design Engineer, you will be at the forefront of designing and developing cutting-edge analog circuits in advanced process nodes. Your work will directly impact Intel's ability to deliver the best-in-class foundational IP and product designs that drive innovation across client, server, and networking technologies. Collaborating with cross-functional teams, you will play a critical role in optimizing performance, power, area, and yield of circuits while pushing the boundaries of what is possible in semiconductor technology.

Key Responsibilities

• Design, develop, and implement analog circuits and mixed-signal IPs, including ADCs, DACs, voltage regulators, and high-speed I/O interfaces.
• Perform circuit-level design, simulation, and optimization to meet power, performance, area, timing, and yield requirements.
• Create and validate floorplans, extract chip parameters, and simulate analog behavior models to ensure robust designs.
• Develop test plans for design verification and evaluate test results to meet specification requirements.
• Collaborate with architecture and layout teams to design circuits that maximize functionality, robustness, and electrical capabilities.
• Conduct tape-out activities for analog and mixed-signal circuits, ensuring successful silicon implementation.
• Analyze and resolve performance and circuit-related issues during design and post-silicon validation phases.
• Serve as a technical interface to process technology, IP engineers, and product teams, leveraging design insights to influence future process node development.

Qualifications

Minimum Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field and 4+ years of experience in analog and mixed-signal circuit design; or Master's degree with 3+ years of experience; or PhD with 1+ years of experience.
• Expertise in analog circuit design, simulation, and verification.
• Proficiency in CMOS technologies and layout understanding for analog circuits.
• Experience with tape-out processes for analog mixed-signal circuits, including ADCs and DACs.
• Knowledge of SoC analog layout design checks and methodologies.

Preferred Qualifications

• Advanced knowledge of high-speed parallel or serial I/O links, clock distribution, or voltage regulator design.
• Experience with PLLs, bandgap references, inductors, transmission lines, and RF or millimeter-wave circuits.
• Strong understanding of power delivery networks (PDN) and integrated power regulators.
• Proven ability to collaborate across teams and influence decisions related to process technology and product development.

Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Oregon, Hillsboro Additional Locations: US, Arizona, Phoenix, US, California, Santa Clara, US, Texas, Austin

Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust N/A

Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.

Annual Salary Range for jobs which could be performed in the US: $141,910.00-269,100.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

• This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.
• Job posting details (such as work model, location or time type) are subject to change.
• ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.