Senior Analog IC Design Engineer — Hybrid

Intel Corporation; Hillsboro (OR); Hybrid; USD 142,000 - 269,000; Full time

Benefits offered by this job

Stock bonuses

Health benefits

Retirement plan

Paid vacation

Job summary

Intel Corporation in Hillsboro, Oregon, is seeking an experienced Analog Circuit Design Engineer to join the AD-FIP within the DTP. You will design and optimize analog/mixed-signal circuits for advanced nodes, contributing to foundational IP for client/server networks.

You will work with cross-functional teams on tape-out readiness, verify layouts, and improve performance, power, area, and yield while pushing semiconductor technology boundaries.

Qualifications

• Bachelor's degree in Electrical/Computer Engineering with 4+ years analog/mixed-signal design
• Experience with ADCs/DACs, PLLs, and high-speed interfaces is desirable
• Familiarity with tape-out flows and analog layout verification for SoC

Responsibilities

• Design, develop, and implement analog/mixed-signal circuits and IPs, including ADCs, DACs, and voltage regulators.
• Perform circuit-level design, simulation, and optimization to meet PPA targets.
• Create floorplans, extract parameters, and validate analog models for robust behavior.
• Develop test plans and verify designs to meet specifications.
• Collaborate with architecture/layout teams to maximize functionality and reliability.
• Lead tape-out activities and resolve post-silicon issues.
• Interface with process technology and product teams to influence future nodes.

Skills

Analog circuit design

Circuit simulation

CMOS technology & analog layout

Tape-out experience

SoC analog layout checks

Education

Bachelor's degree in Electrical/Computer Engineering

Advanced degree (MS/PhD) preferred

Job description

Intel Corporation in Hillsboro, Oregon, is seeking an experienced Analog Circuit Design Engineer to join the AD-FIP within the DTP. You will design and optimize analog/mixed-signal circuits for advanced nodes, contributing to foundational IP for client/server networks.

You will work with cross-functional teams on tape-out readiness, verify layouts, and improve performance, power, area, and yield while pushing semiconductor technology boundaries.