Hybrid SoC Analog & Mixed-Signal Design Engineer

Intel Corporation; Hillsboro, Northern (OR, KY); Hybrid; USD 122,000 - 232,000; Full time

Benefits offered by this job

Stock bonuses

Health insurance

Retirement plan

Vacation

Job summary

Intel Corporation in Hillsboro, Oregon, is seeking a SoC Analog & Mixed-Signal Design Engineer to design and optimize analog/mixed-signal circuits for advanced CMOS processes. You will contribute across the design lifecycle, from architecture to verification, collaborating with architecture and layout teams to deliver robust silicon solutions.

The role emphasizes low-power design, leakage reduction, and high-yield optimization, requiring strong analytical problem-solving and effective

Qualifications

• Bachelor's degree in Electrical Engineering, Electronics, or a related field with 4+ years of experience in analog circuit design.
• Master's degree in Electrical Engineering with 2+ years of experience.
• PhD in Electrical Engineering with 1+ year of educational or work experience.

Responsibilities

• Design, develop, and build analog circuits in advanced CMOS process nodes.
• Create floorplans, perform circuit design, extract chip parameters, and simulate analog behavior models.
• Develop and execute test plans to verify designs against specifications.
• Evaluate test results, verify functionality, and optimize circuits for power, performance, area, timing, and yield.
• Collaborate with architecture, layout, and other cross-functional teams.

Skills

Analog design

Power optimization

Circuit verification

SoC experience

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

PhD in Electrical Engineering

Tools

Analog simulation tools

Job description

Intel Corporation in Hillsboro, Oregon, is seeking a SoC Analog & Mixed-Signal Design Engineer to design and optimize analog/mixed-signal circuits for advanced CMOS processes. You will contribute across the design lifecycle, from architecture to verification, collaborating with architecture and layout teams to deliver robust silicon solutions.

The role emphasizes low-power design, leakage reduction, and high-yield optimization, requiring strong analytical problem-solving and effective