Senior PCIe/CXL RTL Design Engineer (Hybrid)

Rambus; Hillsboro (OR); Hybrid; USD 127,000 - 237,000; Full time

Benefits offered by this job

Health insurance

Employee Stock Purchase Plan

Extra vacation days

Team lunches and breakfasts

Gym membership

Job summary

Rambus seeks a motivated full-time Senior Design Engineer to join the PCIe/CXL IP design team in Hillsboro, OR. The role focuses on architecture and micro-architecture of next-generation IPs, with hands-on SystemVerilog design and FPGA prototyping, collaborating across international teams.

The position offers a hybrid work model with three onsite days and two remote days, along with strong benefits including health insurance, an Employee Stock Purchase Plan, extra vacation days, and team meals.

Qualifications

• Master's degree or PhD in Electrical Engineering, Computer Engineering or equivalent.
• 5+ years of RTL design experience.
• Good English skills and ability to work with an international team.
• Knowledge of PCIe / CXL.

Responsibilities

• Contribute to the architecture and micro-architecture of next generation PCIe / CXL / AMBA controller IP.
• Implement these designs in System Verilog.
• Collaborate with the verification team to verify the IPs.
• Participate in prototyping of the IPs in cutting edge FPGAs.

Skills

RTL Design

PCIe/CXL knowledge

English communication

Education

Master's degree or PhD in Electrical/Computer Engineering

Job description

Rambus seeks a motivated full-time Senior Design Engineer to join the PCIe/CXL IP design team in Hillsboro, OR. The role focuses on architecture and micro-architecture of next-generation IPs, with hands-on SystemVerilog design and FPGA prototyping, collaborating across international teams.

The position offers a hybrid work model with three onsite days and two remote days, along with strong benefits including health insurance, an Employee Stock Purchase Plan, extra vacation days, and team meals.