Front-End CPU Verification Engineer - Unit-Level DV

Tenstorrent; Austin, Santa Clara (TX, CA); Hybrid; USD 100,000 - 500,000; Full time

Job summary

Tenstorrent is seeking a Design Verification Engineer to contribute to unit‑level verification of the RISC‑V CPU front end, including instruction fetch, branch prediction, and related fetch control structures. The role emphasizes building testbenches, generating stimulus, and developing checkers in SystemVerilog, UVM, and C++.

This hybrid role is based in Austin, TX or Santa Clara, CA, with candidacy for various experience levels. Offers align with the level during interviews.

Qualifications

• Front-End verification of CPU front-end blocks using SystemVerilog, UVM, and C++.
• Hands-on unit-level testbench development with precise stimulus and checking.
• Build reusable transactors, predictors, and scoreboards across verification levels.
• Collaborate with RTL designers to trace and fix misspeculation and edge-case fetch bugs.

Responsibilities

• Unit-Level Verification: build and maintain UVM testbenches for instruction fetch units, branch predictors, and related sub-blocks.
• Stimulus generation: develop constrained-random and directed tests for speculation depth, misprediction/redirect flows, fetch bubbles, and cache/TLB interactions.
• C++ integration: develop and maintain C++ reference models and predictors for the verification framework.
• Execution and closure: run verification plans, track functional and code coverage, verify edge cases.

Skills

Front-End experience

Unit-level focus

Reusable design

Collaborative problem solver

Education

Bachelor-level or higher not specified

Tools

SystemVerilog

UVM

C++

Verilator

Job description

Tenstorrent is seeking a Design Verification Engineer to contribute to unit‑level verification of the RISC‑V CPU front end, including instruction fetch, branch prediction, and related fetch control structures. The role emphasizes building testbenches, generating stimulus, and developing checkers in SystemVerilog, UVM, and C++.

This hybrid role is based in Austin, TX or Santa Clara, CA, with candidacy for various experience levels. Offers align with the level during interviews.