Hybrid ASIC Verification Engineer - High-Performance Compute

Waymo; California (MO); Hybrid; USD 175,000 - 215,000; Full time

Benefits offered by this job

Hybrid work schedule

Annual bonus

Equity incentives

Benefits package

Job summary

Waymo's Compute Team is seeking a verification engineer to translate hardware specifications into scalable verification plans, drive testbench development, and validate mission-critical functionality across RTL and software interfaces.

The role requires 3+ years with UVM/SystemVerilog, constrained-random generation, functional coverage, and SystemVerilog Assertions; Python is used for automation. This is a hybrid position reporting to a Silicon Engineering Lead.

Qualifications

• 3+ years of experience building and maintaining complex testbenches using UVM/SystemVerilog.
• Proven track record with constrained-random generation, functional coverage, and SVA (SystemVerilog Assertions).
• Deep understanding of complex digital logic and the ability to debug intricate hardware/software interactions.

Responsibilities

• Translate hardware specifications into comprehensive, scalable verification plans.
• Drive the development of testbenches, reference models, and stimulus to validate functionality and performance.
• Architect and enhance verification environments, contributing to shared tools and reusable methodologies.
• Evaluate, integrate, and verify third-party Verification IP (VIP) to accelerate the development cycle.
• Define and analyze coverage metrics (functional and code) to ensure design readiness and closure.
• Advocate and establish verification best-practices.

Skills

UVM/SystemVerilog

Python

Constrained-random

Functional coverage

SVA

RTL debugging

Strong communication

PCIe

Tools

VIP integration

Job description

Waymo's Compute Team is seeking a verification engineer to translate hardware specifications into scalable verification plans, drive testbench development, and validate mission-critical functionality across RTL and software interfaces.

The role requires 3+ years with UVM/SystemVerilog, constrained-random generation, functional coverage, and SystemVerilog Assertions; Python is used for automation. This is a hybrid position reporting to a Silicon Engineering Lead.