Senior Formal Verification Architect - High-Perf SoC

Waymo; California (MO); Hybrid; USD 204,000 - 259,000; Full time

Benefits offered by this job

Discretionary annual bonus program

Equity incentive plan

Generous Company benefits

Job summary

Waymo is seeking a Silicon Engineer focused on formal verification to drive strategy, build scalable verification environments, and mentor engineers on advanced formal methods. The role emphasizes cross‑functional collaboration across design, architecture, and software, with opportunities to influence automotive compute platforms.

Applicants should have 5+ years of hands-on formal verification on shipping silicon, strong SV, C++/Python skills, and a track record in debugging complex designs.

Qualifications

• BS/MS/PhD in CS/EE or related field, combined with 5+ years of hands-on formal verification experience on shipping silicon products.
• Deep, expert-level proficiency with at least one major commercial formal verification platform (e.g., Cadence JasperGold, Synopsys VC Formal, Mentor Questa Formal)
• High level language proficiency in C++ and/or Python
• Ability to model complex designs in SystemVerilog and advanced SystemVerilog Assertions, including writing complex cut-points and environment models for effective formal proof convergence
• Proven track record in applying advanced formal debug techniques for problem decomposition (e.g., clock domain crossings, abstractions, assume-guarantee reasoning)
• Excellent verbal and written communication skills with the ability to influence cross‑functional teams (Design, Architecture, Software) and drive technical alignment

Responsibilities

• Define and drive formal verification strategy for first-pass silicon success, signing off on complex IP/SoC designs using advanced formal techniques.
• Architect robust FV environments with reusable testbenches, flows, and high-coverage SVA suites.
• Provide technical leadership and mentorship to designers and verification engineers.
• Translate system/IP specs into comprehensive formal verification test plans.
• Maintain and enhance CI, regression flows, and dashboards for FV status and sign-off metrics.
• Apply advanced formal debug methods to tackle challenging verification problems.

Skills

C++ / Python

SystemVerilog & SVAs

Formal verification tools

Cross-functional communication

Formal debug techniques

Education

BS/MS/PhD in CS/EE or related

Tools

Cadence JasperGold

Synopsys VC Formal

Mentor Questa Formal

Job description

Waymo is seeking a Silicon Engineer focused on formal verification to drive strategy, build scalable verification environments, and mentor engineers on advanced formal methods. The role emphasizes cross‑functional collaboration across design, architecture, and software, with opportunities to influence automotive compute platforms.

Applicants should have 5+ years of hands-on formal verification on shipping silicon, strong SV, C++/Python skills, and a track record in debugging complex designs.