ASIC Verification Engineer - UVM/SystemVerilog Focus

Waymo; Mountain View (CA); Hybrid; USD 175,000 - 215,000; Full time

Benefits offered by this job

Annual bonus program

Equity incentive plan

Generous benefits program

Job summary

Waymo is hiring for a verification engineer responsible for building high-performance verification environments for their autonomous vehicle platforms. The role involves collaborating with design teams on hardware specifications and requires significant expertise in UVM/SystemVerilog and Python.

This position follows a hybrid work schedule and offers a competitive salary range of $175,000-$215,000 along with a generous benefits program.

Qualifications

• 3+ years of experience building and maintaining complex testbenches using UVM/SystemVerilog.
• Proven track record with constrained-random generation, functional coverage, and SVA.
• Deep understanding of complex digital logic and debugging skills.

Responsibilities

• Partner with design teams to translate hardware specs into verification plans.
• Drive the development of testbenches and validate mission-critical functionality.
• Architect and enhance verification environments and tools.

Skills

UVM/SystemVerilog experience

Functional coverage

Python proficiency

Analytical skills

Communication skills

Tools

C/C++

PCIe Gen 5/6

DDR5

Job description

Waymo is hiring for a verification engineer responsible for building high-performance verification environments for their autonomous vehicle platforms. The role involves collaborating with design teams on hardware specifications and requires significant expertise in UVM/SystemVerilog and Python.

This position follows a hybrid work schedule and offers a competitive salary range of $175,000-$215,000 along with a generous benefits program.