SerDes Silicon Architect: Transceiver Micro-Architecture Lead

Advanced Micro Devices, Inc.; San Jose (CA); Sur place; USD 180 000 - 240 000; Plein temps

Avantages offerts par ce poste

Benefits at a glance

Résumé du poste

Advanced Micro Devices, Inc. in San Jose, CA is seeking an expert in analog/mixed-signal high-speed PHY design to join the Serdes Technology Group and lead transceiver architecture efforts. The role emphasizes collaboration across teams to deliver robust, scalable designs for next-generation transceivers.

The ideal candidate will drive modeling, verification, and design reviews, interfacing with silicon teams and customers for successful productization and performance optimization.

Qualifications

• Ph.D in electrical engineering with industrial experience or M.S. with relevant industrial experience in optical and/or electrical transceiver design and architecture.
• Excellent communication and documentation skills are required.
• Top-level and block-level electrical/optical link budgeting and modeling.
• Create and maintain high-level design spec and micro-architecture spec documentations.
• Participate in architecture reviews, design reviews, design verification, silicon validation.

Responsabilités

• Lead transceiver micro-architecture definition, modeling, simulation, implementation, and verification: Tx and Rx analog front-end blocks, clocking circuits, DSPs, CDR, adaptation and calibration loops, firmware loops, system level interface.
• Work with pre-tapeout verification for silicon design sign-off and post-silicon validation teams to bring up silicon and analyze volume productization data.

Connaissances

Transceiver architecture

Analog/mixed-signal design

High-speed PHY

Collaboration

Formation

Ph.D in electrical engineering

M.S. with related industrial experience

Description du poste

Advanced Micro Devices, Inc. in San Jose, CA is seeking an expert in analog/mixed-signal high-speed PHY design to join the Serdes Technology Group and lead transceiver architecture efforts. The role emphasizes collaboration across teams to deliver robust, scalable designs for next-generation transceivers.

The ideal candidate will drive modeling, verification, and design reviews, interfacing with silicon teams and customers for successful productization and performance optimization.