Senior DSP Engineer - Data Center Optics & Validation

Broadcom; Wayne (CA); On-site; USD 180,000 - 240,000; Full time

Benefits offered by this job

Medical plans

401(k) match

ESPP

EAP

Paid holidays

Paid sick leave and vacation

Job summary

Broadcom is seeking a Digital Signal Processing and System Validation Engineer to design DSP blocks for next-gen optical data center connectivity products. You will validate ASIC architecture before and after silicon, focusing on high-speed SerDes performance, power, and cost trade-offs.

Roles include translating CDR/equalization into Verilog, using Matlab/Simulink, and leveraging NCVerilog/NCSIM for front-end verification. Strong collaboration across teams is essential for successful delivery.

Qualifications

• MS in Electrical Engineering or Computer Engineering with 10+ years or PhD with 7+ years in DSP design for SerDes.
• Experience in post silicon validation of digital and analog mixed-signal IPs.
• Deep understanding of PAM4/NRZ architectures and high-speed interconnects (100G/200G/400G).
• Translate CDR/equalization architectures into Verilog for synthesis.
• Proficient with Matlab and Simulink; coding in Verilog-HDL/SystemVerilog.
• Exposure to front-end tools such as NCVerilog, NCSIM, Simvision, Spyglass.
• Experience with DFT-friendly RTL, synthesis, CDC, static timing analysis, and parasitic delays.

Responsibilities

• Design DSP blocks for optical data center connectivity products.
• Validate ASIC architecture post- and pre-silicon.
• Develop and verify high-speed SerDes interfaces and related IPs.
• Collaborate across design, verification, and test teams to meet performance and power targets.
• Contribute to design-for-test concepts and RTL optimizations.

Skills

DSP design

SerDes high-speed data center

Verilog/SystemVerilog

Matlab/Simulink

Front end tools NCVerilog

DFT RTL

Synthesis/CDC/STA

SDF simulations

Analog/mixed-signal IP validation

SI/PI modeling

Education

MS in Electrical Engineering or Computer Engineering

PhD in Electrical/Computer Engineering

Tools

Verilog-HDL/SystemVerilog

Job description

Broadcom is seeking a Digital Signal Processing and System Validation Engineer to design DSP blocks for next-gen optical data center connectivity products. You will validate ASIC architecture before and after silicon, focusing on high-speed SerDes performance, power, and cost trade-offs.

Roles include translating CDR/equalization into Verilog, using Matlab/Simulink, and leveraging NCVerilog/NCSIM for front-end verification. Strong collaboration across teams is essential for successful delivery.