ASIC Digital Design Implementation Engineer — Contract

Saige Partners LLC; San Jose (CA); On-site; USD 96,000 - 138,000; Full time

Job summary

Saige Partners in San Jose, CA is seeking a Digital Design Implementation Engineer to join its SoC R&D team. You will drive ASIC design implementation across RTL-to-signoff-quality silicon, focusing on logic synthesis, STA, and place-and-route in a fast-paced semiconductor environment.

The role emphasizes collaboration with RTL, DFT, and physical design teams, development of flows and automation scripts, and ongoing PPA optimization to improve timing, power, and area for high-speed wireless and

Qualifications

• Bachelor's degree in EE/CE or related field.
• At least 2 years hands-on ASIC design implementation experience.
• Experience with STA, logic synthesis, or PnR.
• Proficiency with Tcl/Python/Perl/shell scripting.

Responsibilities

• Perform ASIC design implementation including synthesis, STA, and PnR.
• Develop and optimize implementation flows and automation scripts.
• Drive timing, power, and area closure to meet objectives.
• Execute timing signoff and validate SDCs; analyze timing reports.
• Collaborate with RTL, DFT, and physical design teams.
• Support silicon bring-up, validation, and commercialization.
• Improve design quality and engineering workflows.

Skills

ASIC design implementation

STA (Static Timing Analysis)

Logic synthesis

Place & Route (PnR)

Timing constraints / SDC

Scripting (Tcl, Python)

Problem solving

Teamwork & communication

Education

Bachelor's degree in Electrical/Computer Engineering

Tools

Synopsys Design Compiler

Fusion Compiler

PrimeTime

Cadence Genus

Cadence Innovus

Cadence Tempus

Job description

Saige Partners in San Jose, CA is seeking a Digital Design Implementation Engineer to join its SoC R&D team. You will drive ASIC design implementation across RTL-to-signoff-quality silicon, focusing on logic synthesis, STA, and place-and-route in a fast-paced semiconductor environment.

The role emphasizes collaboration with RTL, DFT, and physical design teams, development of flows and automation scripts, and ongoing PPA optimization to improve timing, power, and area for high-speed wireless and