Head of Physical Design, 3D Memory AI ASICs

Acceler8 Talent; San Francisco (CA); On-site; USD 350,000 - 600,000; Full time

Job summary

Acceler8 Talent is partnering with a startup to hire a visionary Director of Physical Design for a leading 3D-memory AI accelerator platform. You will guide full-chip PD from netlist to GDSII, drive floorplanning, CTS, routing, timing closure and PD verification, and coordinate with architecture, RTL, DFT, packaging and foundry teams.

You will set PD methodology, lead team planning and optimize power integrity, reliability and timing across advanced nodes, including 3nm/5nm.

Qualifications

• 15–20 years of ASIC/SoC Physical Design experience with multiple tapeouts.
• Expert PD tools, flows and advanced process nodes (3nm/5nm/7nm)
• Experience with NoC/Fabric/AXI interconnect physical implementation; placement and routing of high-performance on-chip networks.
• DFT-aware physical design; scan chain routing, BIST controller placement, JTAG/boundary scan integration and test-mode physical constraints.

Responsibilities

• Lead full-chip physical design from netlist to GDSII signoff for AI accelerators, ensuring PPA and schedule goals.
• Own floorplanning, CTS, routing, timing closure and physical verification; develop PD flows for Innovus/Genus.
• Drive team planning, external Design Service partners, resource allocation and milestone reviews for tapeouts.
• Collaborate with SoC, DFT, Packaging and Foundry teams to solve integration challenges, including 3D-memory connectivity.
• Develop and review power grid strategies; perform IR drop and EM analysis using Cadence Voltus or ANSYS RedHawk; account for TSV-based delivery.
• Implement scan chain routing, BIST controller placement, JTAG/boundary scan integration; manage test-mode constraints with DFT Lead.
• Own DRC/LVS/ERC signoff using Mentor Calibre or IC Validator; ensure clean tapeouts across all blocks.

Skills

Leadership

Communication

Project management

Team leadership

Education

B.E./M.S. in Electrical Engineering, VLSI or related discipline

Tools

Innovus

Genus

Mentor Calibre

IC Validator

Cadence Voltus

ANSYS RedHawk

Job description

Acceler8 Talent is partnering with a startup to hire a visionary Director of Physical Design for a leading 3D-memory AI accelerator platform. You will guide full-chip PD from netlist to GDSII, drive floorplanning, CTS, routing, timing closure and PD verification, and coordinate with architecture, RTL, DFT, packaging and foundry teams.

You will set PD methodology, lead team planning and optimize power integrity, reliability and timing across advanced nodes, including 3nm/5nm.