HBM SoC RTL Design Intern — High-Impact Hardware

Micron Technology; Folsom (CA); On-site; USD 54,000 - 69,000; Full time

Job summary

Micron Technology in the United States is seeking an SoC Design Engineer Intern to contribute to RTL design for HBM logic within the Heterogeneous Integration Group. You will work with architecture, verification, physical design, firmware, and product teams to deliver high-performance, power-efficient RTL blocks.

You will gain experience across the RTL-to-GDS flow, pre/post-silicon validation, and collaborate on tool-enabled workflows to improve efficiency and quality in a world‑leading memory

Qualifications

• Pursuing a Bachelor's or master's degree in electrical engineering, computer engineering, or related field.
• Cannot graduate before December 2027; available for a 6‑month internship.

Responsibilities

• Design and implement RTL for SoC-level blocks and subsystems used in HBM logic die.
• Integrate internal and third-party IP (controllers, NOC, RAS, MBIST, interfaces, adapters, buffers, PHY-adjacent logic).
• Collaborate with SoC architects to translate specs into high-quality RTL implementations.
• Participate in SoC-level integration activities, including clocking, reset, power intent, and configuration infrastructure.
• Assist with pre-silicon validation and post-silicon bring-up, including root-cause analysis of silicon issues.
• Contribute to design documentation, block specs, and design reviews.
• Collaborate with Product Engineering, Test, Process Integration, and Manufacturing for robust builds.

Skills

SystemVerilog/Verilog

RTL-to-GDS flow

EDA tools (Cadence/Synopsys/Siemens)

Programming/scripting (Python/TCL/Perl

SoC integration methodologies

Education

Bachelor's or Master's in Electrical/Computer Engineering

Job description

Micron Technology in the United States is seeking an SoC Design Engineer Intern to contribute to RTL design for HBM logic within the Heterogeneous Integration Group. You will work with architecture, verification, physical design, firmware, and product teams to deliver high-performance, power-efficient RTL blocks.

You will gain experience across the RTL-to-GDS flow, pre/post-silicon validation, and collaborate on tool-enabled workflows to improve efficiency and quality in a world‑leading memory