HBM SoC Architect & RTL Design Engineer (SMTS)

Micron Technology, Inc.; Richardson (TX); On-site; USD 177,000 - 334,000; Full time

Benefits offered by this job

Medical, dental and vision plans

Paid time off & holidays

Bonuses & equity (possible)

Job summary

Micron Technology, Inc. in the United States is seeking an experienced SoC Architecture and Design Engineer to shape RTL for HBM logic die and optimize memory subsystems.

You will collaborate with architecture, design, verification, physical design, firmware, and product teams to build high‑performance, power‑aware blocks that meet aggressive targets. This hands‑on role requires strong RTL implementation, IP integration, pre/post‑silicon support, and clear design documentation.

Qualifications

• Bachelor's or master's degree in electrical/computer engineering or related field.
• Minimum 15 years of related experience.
• Proficiency in SystemVerilog/Verilog; RTL-to-GDS flow; Synthesis and timing analysis.

Responsibilities

• Architect, design and implement RTL for SoC-level blocks and subsystems used in HBM logic die.
• Architect and design memory sub-systems including IP selection and integration, bus/protocol choices, and power/area optimization.
• Integrate internal and third-party IP (controllers, NOC, MBIST, interfaces, adapters, buffers, PHY-adjacent logic).
• Translate architectural specs into high-quality RTL implementations.
• Assist with pre-silicon validation and post-silicon bring-up; root-cause analysis of silicon issues.
• Contribute to design documentation, block specs, and design reviews; collaborate with Product Eng, Test, Process, and Manufacturing.

Skills

SystemVerilog/Verilog

RTL design

Python scripting

TCL scripting

Shell scripting

Education

Bachelor's or Master's in Electrical/Computer Engineering

Tools

Cadence

Synopsys

Siemens

Job description

Micron Technology, Inc. in the United States is seeking an experienced SoC Architecture and Design Engineer to shape RTL for HBM logic die and optimize memory subsystems.

You will collaborate with architecture, design, verification, physical design, firmware, and product teams to build high‑performance, power‑aware blocks that meet aggressive targets. This hands‑on role requires strong RTL implementation, IP integration, pre/post‑silicon support, and clear design documentation.