HBM Memory Design Engineer - Circuit & RTL Expert

Micron Technology, Inc; Richardson (TX); On-site; USD 120,000 - 180,000; Full time

Job summary

Micron Technology, Inc. in Richardson, TX seeks a Circuit/Memory Design Engineer for HBM to design and analyze digital and analog circuits used in next-generation memory products.

You will collaborate with global teams to optimize manufacturability, performance and yield across tape-out cycles. The role involves parasitic modeling, layout oversight, and verification using Verilog, FastSPICE, and HSPICE, with opportunities to impact technology scaling and time-to-market.

Qualifications

• Bachelor’s degree in Electrical Engineering or equivalent practical experience.
• 4+ years of relevant experience with a Bachelor's degree, or 2+ years with a Master’s degree.
• Extensive knowledge of CMOS circuit design and semiconductor device physics.
• Experience with schematic entry, Verilog, FastSPICE, and HSPICE simulations.
• Strong understanding of timing, area, power, and complexity trade-offs in DRAM or mixed-signal design.

Responsibilities

• Contribute to new product opportunities by supporting circuit design, layout, and optimization for memory and logic or analog circuits.
• Perform parasitic modeling and support design validation, including reticle experiments and required tape-out revisions.
• Oversee and manage the layout process, including floor-planning, placement, and routing.
• Perform verification using modeling, simulation and AI assisted analysis with industry-standard simulators.
• Collaborate across teams to drive standardization and shared design success.

Skills

CMOS circuit design

Verilog

Schematic entry

HSPICE

FastSPICE

Timing/power trade-offs

Education

Bachelor's degree in Electrical Engineering

Tools

HSPICE

FastSPICE

CAD/layout tools

Job description

Micron Technology, Inc. in Richardson, TX seeks a Circuit/Memory Design Engineer for HBM to design and analyze digital and analog circuits used in next-generation memory products.

You will collaborate with global teams to optimize manufacturability, performance and yield across tape-out cycles. The role involves parasitic modeling, layout oversight, and verification using Verilog, FastSPICE, and HSPICE, with opportunities to impact technology scaling and time-to-market.