HBM IO Architect — Analog & Mixed-Signal High-Speed

Micron Technology; Richardson (TX); On-site; USD 140,000 - 210,000; Full time

Job summary

Micron Technology in Richardson, TX, seeks an experienced HBM Architecture Engineer to define and drive the architecture of high-speed analog and mixed-signal IO subsystems for HBM products. The role emphasizes PHY IO architecture, timing methodology, analog calibration schemes, and silicon learning frameworks enabling top-tier bandwidth and power efficiency.

You will collaborate across Design, Product Engineering, Modeling, Verification, Packaging, and System Architecture to translate concepts

Qualifications

• MS or PhD in Electrical Engineering or related field.
• 7+ years in semiconductor design, architecture, or technology development.
• Expertise in analog and mixed-signal IO design and architecture.
• Deep knowledge of high-speed transmitter/receiver, clocking, timing architectures.

Responsibilities

• Define and drive next-gen HBM PHY and IO architecture balancing performance, power, area, reliability.
• Architect high-performance transmit and receive paths, including clocking, signaling, equalization, timing alignment, and interface optimization.
• Define and optimize analog calibration architectures, including impedance calibration, reference voltage calibration, timing calibration, and adaptive tuning methodologies.
• Develop and maintain IO timing budgets, design targets, and margin methodologies across process, voltage, temperature, and package variations.

Skills

Analog IO

Mixed-signal

High-speed design

Technical communication

Semiconductor architecture

Education

MS or PhD in Electrical Engineering

Tools

Simulation tools

Modeling tools

Job description

Micron Technology in Richardson, TX, seeks an experienced HBM Architecture Engineer to define and drive the architecture of high-speed analog and mixed-signal IO subsystems for HBM products. The role emphasizes PHY IO architecture, timing methodology, analog calibration schemes, and silicon learning frameworks enabling top-tier bandwidth and power efficiency.

You will collaborate across Design, Product Engineering, Modeling, Verification, Packaging, and System Architecture to translate concepts