Kernel Engineer, Custom Silicon for High-Perf AI Compute

River AI Inc.; Palo Alto, Austin (CA, TX); On-site; USD 210,000 - 420,000; Full time

Benefits offered by this job

Health, dental, and vision benefits

Equity

Relocation support

Job summary

River AI Inc. is seeking a Kernel Engineer (Custom Silicon) to build the foundational compute engine for our high-performance hardware. You will create C++-based code-generation frameworks that emit optimized ISA assembly and push the limits of our architecture for DL operations like GEMMs and attention.

You will collaborate with compiler, silicon, and research teams to maximize ALU utilization, optimize memory, and ensure mathematical correctness through rigorous validation. Relocation possible.

Qualifications

• Bachelor's degree and 5+ years in low-level performance programming.
• Experience with hardware programming models and optimized kernels.
• Strong knowledge of computer architecture, vector units, memory hierarchies.
• Proficiency in modern C++ for meta-programming and code generation.

Responsibilities

• Design and build C++ code-generation frameworks for emitting optimized ISA assembly.
• Optimize core DL primitives (GEMM/MatMul, Attention, Convolutions) for custom silicon.
• Tune instruction scheduling, register allocation, and software pipelines.
• Design tiling and data-movement strategies to maximize SRAM use.
• Collaborate with RTL/architecture teams to influence ISA and future units.
• Benchmark and validate against simulators and hardware with performance counters.

Skills

Low-level programming

High-performance computing

C++ proficiency

Mathematics literacy

Collaborative mindset

Education

Bachelor’s degree in Computer Engineering, Computer Science, Electrical Engineering, or related field

Tools

CUDA

Triton

CUTLASS

Custom ISA

Job description

River AI Inc. is seeking a Kernel Engineer (Custom Silicon) to build the foundational compute engine for our high-performance hardware. You will create C++-based code-generation frameworks that emit optimized ISA assembly and push the limits of our architecture for DL operations like GEMMs and attention.

You will collaborate with compiler, silicon, and research teams to maximize ALU utilization, optimize memory, and ensure mathematical correctness through rigorous validation. Relocation possible.