Performance Engineer, Hardware

River AI; Iowa; On-site; USD 200,000 - 420,000; Full time

Benefits offered by this job

Health, dental, and vision benefits

Unlimited PTO

Relocation support

Job summary

River AI is building high-performance hardware for AI workloads and seeks a Hardware Performance Engineer to model, simulate, and optimize our accelerator stack. You will develop C++/SystemC models, explore micro-architectures, and collaborate across RTL, compiler, and software teams to push IPC and efficiency in pre-silicon stages.

This role offers competitive compensation and equity, with visa sponsorship for exceptional candidates, and is based in the United States with options around Austin

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering or Computer Science with 5+ years of industry experience in advanced process nodes (7nm or below).
• Proficient in C/C++ or event-driven simulation environments like SystemC.
• Experience with compilers (LLVM/GCC/XLA) and high-performance kernels (CUDA/Triton) interacting with ISA.
• Strong knowledge of computer architecture for at least one chip style (SoCs/CPUs/GPUs/AI accelerators).
• Experience profiling hardware with performance counters and trace analysis tools.
• Collaborative mindset for cross-team co-design with engineers.

Responsibilities

• Simulator Development: design high-performance models of complex hardware using C++ and SystemC.
• Micro-architectural Exploration: run what-if studies on cache, branches, pipelines, and matmul shaping.
• Workload Characterization: profile AI kernels to create representative traces for stress-testing models.
• HW/SW Co-Design: optimize software mapping to hardware with compiler and kernel teams.
• Performance Correlation: compare models to RTL/pre-silicon emulators and ensure accuracy.
• Bottleneck Analysis: identify ILP limits and bandwidth bottlenecks affecting utilization.

Skills

Simulator development

Micro-architectural exploration

Workload characterization

HW/SW co-design

Performance correlation

Bottleneck analysis

Education

Bachelor's in Electrical/Computer Engineering or Computer Science

Tools

C++

SystemC

LLVM

GCC

CUDA

Triton

QEMU

Job description

At River AI, our mission is to create personal AI owned and shaped by each individual. To achieve this, we are rewriting the entire stack from scratch: personal hardware for local inference, custom training infrastructure, next-generation UIs, and frontier deep learning research.

Who we are

We are scientists, engineers, and builders from the industry's top tech companies and AI labs. We bring a proven track record of scaling consumer systems for hundreds of millions of users and architecting the pre-training infrastructure behind today's frontier models.

About the Role

We are seeking exceptional hardware performance engineers to architect, model, and correlate high-performance custom silicon. You will develop high-fidelity simulators to predict how our AI accelerator architecture and SoC system will handle real-world AI models. You will take ownership of performance models, ISA and kernel optimization, and FPGA emulators for software development. You will be collaborating both up and down the stack with compiler, IR, and software teams, as well as with RTL design engineers.

What You’ll Do

• Simulator Development: Design and implement high-performance and functional models of complex hardware using C++ and/or SystemC.
• Micro-architectural Exploration: Conduct "what-if" studies to evaluate architectural changes (e.g., cache sizes, branch predictors, pipeline depths, scatter/gather, matmul shaping) and their impact on IPC, MFU, TTFT, and total execution time.
• Workload Characterization: Analyze and profile AI kernels and software stacks to generate representative traces that stress-test the hardware models.
• HW/SW Co-Design: Collaborate with compiler and kernel teams to optimize software mapping to hardware, ensuring the architecture supports emerging algorithmic breakthroughs efficiently.
• Performance Correlation: Validate the performance model against RTL and pre-silicon emulators to ensure the model’s accuracy remains within strict tolerance levels.
• Bottleneck Analysis: Identify and quantify system-level bottlenecks, ranging from instruction-level parallelism (ILP) limits to bandwidth throttling to utilization.

Skills and Qualifications

Minimum Qualifications:

• Bachelor’s degree in Electrical Engineering or Computer Engineering or Computer Science, and 5+ years practical industry experience working with advanced process nodes (7nm or below).
• Expert proficiency in C/C++ or event-driven simulation environments like SystemC
• Hands-on experience with how compilers transform code (LLVM/GCC/XLA) and how high-performance kernels (CUDA/Triton) interact with the underlying ISA.
• Expert knowledge in Computer Architecture of at least one style of chip, including SoCs, CPUs, GPUs, or AI accelerators
• Experience with profiling hardware with performance counters, hardware profilers, and trace analysis tools to dissect application behavior.
• A highly collaborative mindset to push boundaries and co-design effectively with other engineers.

Preferred Qualifications: (We encourage you to apply even if you don't meet all of these)

• Hands-on experience in pre-silicon RTL/emulator and/or post-silicon performance validation
• Knowledge or experience of QEMU models for pre-silicon software development
• Proficiency in scripting for data post-processing, visualization of simulation results, and automation of massive regression suites.

Logistics & Benefits

• Location: This role is based in Austin, Texas or Palo Alto, California.
• Compensation: Depending on background, skills, and experience, the expected annual salary range for this position is $200,000 - $420,000 USD, plus equity.
• Visa Sponsorship: We sponsor visas. We can't guarantee success for every candidate or role, but if you're the right fit, we're committed to working through the visa process.
• Benefits: River AI offers generous health, dental, and vision benefits, unlimited PTO, and relocation support as needed.