Hardware ASIC Packaging SI/PI Simulation and Design Lead (Remote)

Ladders; United States; Remote; USD 187,000 - 268,000; Full time

Benefits offered by this job

Hybrid work option

Onsite preference in San Jose, CA

Mentorship opportunities

Cutting-edge ASIC packaging

Job summary

Ladders' client is seeking a Hardware ASIC Packaging SI/PI Simulation and Design Lead to guide high-speed packaging efforts for advanced semiconductor hardware in a remote setting. You will partner across layout, architecture, system, and vendors to resolve complex challenges from conception to high-volume release.

You will lead design decisions, establish SI/PI design rules, perform simulations, and mentor engineers to strengthen engineering execution across the organization.

Qualifications

• Bachelor's degree in Electrical Engineering with 8+ years of experience, or advanced degrees with reduced years.
• Expertise in high-speed signaling and SERDES architectures (56G PAM4).
• Proficiency with SI/PI simulations and physical validation tools.

Responsibilities

• Develop and implement design rules for ultra-high-speed signaling to support power and performance goals.
• Analyze substrate signal and power integrity with layout teams to identify optimal solutions.
• Design and document ASIC packages for high-volume release, including post-layout extraction.
• Collaborate with system partners and vendors to resolve SI/PI issues.
• Define processes and tools for complex ASIC and package development.
• Lead architecture discussions and IC design reviews for high-performance ASICs.
• Mentor junior engineers and drive continuous improvement across teams.

Skills

High-speed design

Signal integrity

Power integrity

SI/PI methods

Transmission Line Theory

Impedance analysis

IC design reviews

Mentorship

Education

Bachelor's in Electrical Engineering

Master's in Electrical Engineering

PhD in Electrical Engineering

Tools

Cadence Sigrity

Ansys HFSS

Cadence APD

Ansys EM flows

SPICE

Job description

For our client, we are seeking a Hardware ASIC Packaging SI/PI Simulation and Design Lead to join the team of a leader in the Telecommunications & Hardware space.

This role will lead high-speed ASIC packaging efforts with a strong focus on signal integrity and power integrity for advanced semiconductor hardware. You will partner closely with layout, architecture, system, and vendor teams to resolve complex technical challenges and guide design decisions from early concept through high-volume release. The position also combines technical leadership, process development, and mentorship to help strengthen engineering execution across the organization.

Location: Remote

Compensation: $186,900 – $267,700 annually

Responsibilities

• Develop and implement design rules for ultra-high-speed signaling to support power and performance goals.
• Analyze substrate signal and power integrity while collaborating with layout teams to identify optimal solutions.
• Design and document ASIC packages for high-volume release, including post-layout extraction.
• Work with system partners and vendors to resolve complex technical issues in power and signal integrity.
• Define processes and tools for complex ASIC and package development.
• Lead discussions on chip architecture and high-performance ASIC design, including detailed IC design reviews.
• Mentor junior engineers and promote a culture of continuous improvement across engineering teams.

Qualifications

• Bachelor's degree in Electrical Engineering with 8+ years of experience, or a Master's degree with 6+ years of experience, or a PhD with 3+ years of experience in signal and power integrity.
• Proficiency in high-speed design principles, including Transmission Line Theory and impedance network analysis for 56G PAM4 SerDes architectures.
• Experience with SI/PI simulations using tools such as Cadence Sigrity and Ansys HFSS.
• Skill in conducting layout reviews and physical validation with Cadence APD and Ansys EM flows.
• Familiarity with SPICE for circuit-level analysis and performance validation.

Benefits

• Opportunity for hybrid work with onsite preference in San Jose, CA.
• Engagement in cutting-edge ASIC packaging development.
• Collaboration with diverse teams and industry partners.
• Mentorship opportunities to influence junior engineers and teams.
• Culture of continuous improvement and design reviews.

Our client is an equal opportunity employer. We encourage you to apply even if you don’t meet every qualification—your background could be exactly what this team needs.