Graviton SoC Design Engineer - RTL & Verification Lead

Annapurna Labs; Illinois; In loco; USD 140.000 - 190.000; Tempo pieno

Descrizione del lavoro

Annapurna Labs is seeking experienced engineers for its chip design team in Illinois to advance the Graviton product line. You will contribute to SoC development, RTL implementation, and verification across a full silicon cycle, collaborating with product, design, and software teams to deliver scalable cloud-grade processors.

Join a fast-paced environment shaping the future of cloud infrastructure, leveraging Verilog/SystemVerilog, CPU architecture knowledge, and IP integration experience to

Competenze

• BSc in Electrical Engineering / Computer Engineering / Computer Science (required).
• Knowledge of digital logic systems and computer architecture.
• Please include your CV and a grade sheet in a single PDF file.

Mansioni

• Drive SoC development from micro-architecture definition through tape-out.
• Design and implement RTL blocks within a complex semiconductor platform.
• Perform system-level debugging and performance analysis.
• Lead pre and post-silicon verification activities for your design areas.
• Define and execute IP integration strategies.
• Ensure quality and reliability standards across your deliverables.
• Collaborate with cross-functional teams including Product Definition, Verification, Physical Design, and Software Engineering

Conoscenze

RTL design

Verilog/SystemVerilog

CPU architecture

IP integration

English proficiency

Formazione

BSc in Electrical Engineering / Computer Engineering / Computer Science

Descrizione del lavoro

Annapurna Labs is seeking experienced engineers for its chip design team in Illinois to advance the Graviton product line. You will contribute to SoC development, RTL implementation, and verification across a full silicon cycle, collaborating with product, design, and software teams to deliver scalable cloud-grade processors.

Join a fast-paced environment shaping the future of cloud infrastructure, leveraging Verilog/SystemVerilog, CPU architecture knowledge, and IP integration experience to