Design Verification Lead, SoC & Nitro Systems

Amazon Web Services (AWS); Illinois; On-site; USD 140,000 - 180,000; Full time

Job summary

Annapurna Labs Ltd. is seeking a Design Verification Team Lead to spearhead verification of complex SoC sub-systems for the Nitro family, driving advanced verification methods and ensuring silicon quality before tapeout.

You will collaborate across hardware and software teams, shaping verification strategies from product definition to post-silicon validation, with emphasis on networking workloads and high-performance interfaces.

Qualifications

• 8+ years of experience in design verification of complex SoC or ASIC projects.
• Strong communication skills to collaborate across design, software, and physical design teams.
• Proven track record verifying IO sub-systems, interconnect fabrics, or system-level blocks.
• Deep expertise in UVM/SystemVerilog-based verification environments.
• Experience driving verification from product definition through post-tapeout silicon validation.
• Experience with performance verification methodologies alongside functional correctness.

Responsibilities

• Develop and execute verification plans for IO sub-systems - covering interconnect protocols, peripheral interfaces, and system-level integration with networking flows (ENA/EFA).
• Verify IO sub-system features, including interconnect protocols and various accelerator engines.
• Develop and debug C embedded SW as part of hardware-software integration verification.
• Build and maintain UVM-based verification environments for various clusters and sub-systems.
• Verify ARM advanced interconnect protocols (AMBA CHI/ACE/AXI) ensuring correct coherency transactions, performance verification, and protocol compliance.
• Verify the IO virtualization SMMU/TLB operations, page table walks, translation granules, and memory attributes (cache-ability, share-ability).
• Develop constrained-random and directed test strategies targeting corner cases in IO protocol hazards, coherency races, and system boundary conditions.
• Drive coverage closure using functional coverage models, assertion-based verification, and formal methods where applicable.
• Contribute to performance verification - ensuring micro-architectural implementations meet performance targets alongside correctness.

Skills

UVM/SystemVerilog

Embedded C/C++

SoC/ASIC verification

HW-SW co-verification

Tools

UVM

SystemVerilog

Job description

Annapurna Labs Ltd. is seeking a Design Verification Team Lead to spearhead verification of complex SoC sub-systems for the Nitro family, driving advanced verification methods and ensuring silicon quality before tapeout.

You will collaborate across hardware and software teams, shaping verification strategies from product definition to post-silicon validation, with emphasis on networking workloads and high-performance interfaces.