Lead, Nitro SoC Design Verification

Amazon Web Services (AWS); Illinois; On-site; USD 180,000 - 240,000; Full time

Job summary

Annapurna Labs Ltd. is seeking an experienced Design Verification Team Lead to drive verification of complex SoC sub-systems for AWS Nitro.

You will shape verification strategies from product definition through post-tapeout, collaborating with software and physical design teams to ensure robust silicon and high networking performance. You will build and maintain UVM-based environments, verify ARM interconnect protocols, and guide constrained-random and directed test strategies while pushing for

Qualifications

• 8+ years in design verification of complex SoC/ASIC projects.
• Strong communication across design, software and physical teams.
• Proven track record leading IO-subsystem verification.
• Deep expertise in UVM/SystemVerilog environments.
• Experience from product definition through post-tapeout.
• Experience with performance verification alongside functional correctness.

Responsibilities

• Develop and execute verification plans for IO sub-systems and interconnects.
• Verify IO sub-system features and accelerator engines.
• Develop and debug C embedded SW as part of HW-SW verification.
• Create and maintain UVM-based verification environments.
• Verify ARM interconnect protocols AMBA CHI/ACE/AXI for coherency.
• Verify IO virtualization SMMU/TLB and page-walks.
• Develop constrained-random and directed test strategies for IO protocols.
• Drive coverage with functional coverage, assertions, and formal methods.
• Contribute to performance verification ensuring timing and throughput targets.

Skills

UVM/SystemVerilog

Verification leadership

IO sub-systems

Strong communication

Performance verification

Tools

UVM

SystemVerilog

Job description

Annapurna Labs Ltd. is seeking an experienced Design Verification Team Lead to drive verification of complex SoC sub-systems for AWS Nitro.

You will shape verification strategies from product definition through post-tapeout, collaborating with software and physical design teams to ensure robust silicon and high networking performance. You will build and maintain UVM-based environments, verify ARM interconnect protocols, and guide constrained-random and directed test strategies while pushing for