Lead Formal Verification Engineer: Architecture to Sign-off

Annapurna Labs; Illinois; On-site; USD 140,000 - 190,000; Full time

Job summary

Annapurna Labs Ltd. in Illinois is seeking an L5 Formal Verification Engineer to own FV for blocks within Graviton or Nitro subsystems, from architecture to sign-off. You will mentor other engineers and help shape verification methodologies in a fast-paced AWS environment.

You will work with senior leaders, explore AI-enhanced verification flows, and collaborate with design teams to ensure provable RTL and robust silicon blocks.

Qualifications

• 5+ years of hands-on formal verification experience.
• Strong knowledge of SystemVerilog Assertions (SVA).
• Hands-on experience with industry formal tools.
• Owned formal closure on complex blocks.

Responsibilities

• Own formal verification of your blocks from architecture through sign-off.
• Write the formal plan and define what must be proven.
• Build formal environments covering FPV, sequential equivalence, connectivity, X-prop, security, and liveness.
• Solve convergence problems with abstraction, invariants, and decomposition.
• Report clearly what is proven, what is bounded, and what is still open.
• Work with design teams to define verification intent and improve design quality.
• Bring new techniques, including AI and agentic flows, into team flows.

Skills

Formal verification

SystemVerilog Assertions (SVA)

Hands-on verification experience

Mentoring

Formal closure

Education

Bachelor's degree in Electrical Engineering

Bachelor's degree in Electrical Engineering or Computer Science

Tools

Industry formal tools

Job description

Annapurna Labs Ltd. in Illinois is seeking an L5 Formal Verification Engineer to own FV for blocks within Graviton or Nitro subsystems, from architecture to sign-off. You will mentor other engineers and help shape verification methodologies in a fast-paced AWS environment.

You will work with senior leaders, explore AI-enhanced verification flows, and collaborate with design teams to ensure provable RTL and robust silicon blocks.