Graph Compiler Engineer: Fusion & Performance Optimization

Meta; New York (NY); On-site; USD 184,000 - 257,000; Full time

Job summary

Meta is seeking a Compiler Engineer in Graph Compiler Performance Optimization to design and implement passes within the PyTorch Inductor FX IR pipeline for MTIA. You will profile DL models, reduce bottlenecks, and drive kernel-level and memory-performance improvements on MTIA hardware.

Collaborate with AI researchers and hardware engineers to ensure portable, scalable compiler optimizations across MTIA generations, delivering high-throughput AI workloads out of the box.

Qualifications

• Experience in compiler development, performance optimization, or accelerating deep learning models on hardware architectures.
• Understanding of deep learning model execution (graphs, operators, data flow) and compiler transformations impact on performance.
• Bachelor's degree in CS/CE or equivalent practical experience.

Responsibilities

• Design, implement, and validate graph-level compiler optimization passes targeting PyTorch Inductor FX IR for MTIA.
• Profile and analyze DL models to identify graph-level bottlenecks and develop compiler solutions.
• Develop and extend fusion strategies to maximize MTIA hardware utilization across generations.
• Implement memory optimizations to reduce latency and improve bandwidth in MTIA workloads.
• Build performance analysis tooling to accelerate optimization iterations.
• Collaborate with hardware teams on HW-SW co-design for new silicon capabilities.

Skills

C/C++

Python

Compiler development

Performance optimization

PyTorch internals

MLIR/XLA

Hardware acceleration

Deep learning frameworks

Education

Bachelor's degree in CS/CE or related

Tools

PyTorch

FX IR

Inductor

TorchDynamo

LLVM

XLA

TVM

MLIR

Glow

Job description

Meta is seeking a Compiler Engineer in Graph Compiler Performance Optimization to design and implement passes within the PyTorch Inductor FX IR pipeline for MTIA. You will profile DL models, reduce bottlenecks, and drive kernel-level and memory-performance improvements on MTIA hardware.

Collaborate with AI researchers and hardware engineers to ensure portable, scalable compiler optimizations across MTIA generations, delivering high-throughput AI workloads out of the box.