Compiler Engineer

Oho Group; San Francisco (CA); On-site; USD 180,000 - 260,000; Full time

Job summary

Oho Group in San Francisco is seeking a seasoned compiler engineer to own optimizations that transform models and graphs into efficient programs for a new accelerator architecture. You will shape the compiler mid-stack, focusing on performance-critical paths rather than maintaining an existing toolchain.

You’ll work across MLIR-based pipelines, optimize data movement, parallelism and hardware utilization, and collaborate with architecture, code-generation and runtime engineers to map ML

Qualifications

• Strong C++ and compiler engineering experience.
• Hands-on knowledge of LLVM, MLIR or comparable compiler infrastructure
• Experience with graph optimization, IR transformations or lowering
• Ability to reason across compiler decisions and hardware behavior
• Experience with PyTorch compilation, Triton, GPUs, AI accelerators, memory optimization or hardware/software co-design would be particularly valuable.

Responsibilities

• Design graph and IR-level compiler optimizations
• Develop transformation, fusion, scheduling and memory-planning passes
• Lower workloads through MLIR-based compilation pipelines
• Optimize data movement, parallelism and accelerator utilization
• Analyze generated programs and eliminate performance bottlenecks
• Collaborate with architecture, code-generation and runtime engineers
• Help define how ML workloads should map onto the underlying hardware

Skills

C++

LLVM/MLIR

Graph optimization

IR transformations

Lowering

PyTorch compilation

Triton

GPUs

Job description

We’re working with an AI software company building a new compiler and software stack for high-performance accelerated computing.

This role sits in the middle of the compiler, transforming models and computational graphs into efficient programs for a new accelerator architecture. You’ll own optimizations that materially affect workload performance rather than maintaining an established toolchain.

What you’ll work on

• Design graph and IR-level compiler optimizations
• Develop transformation, fusion, scheduling and memory-planning passes
• Lower workloads through MLIR-based compilation pipelines
• Optimize data movement, parallelism and accelerator utilization
• Analyze generated programs and eliminate performance bottlenecks
• Collaborate with architecture, code-generation and runtime engineers
• Help define how ML workloads should map onto the underlying hardware

What we’re looking for

• Strong C++ and compiler engineering experience
• Hands‑on knowledge of LLVM, MLIR or comparable compiler infrastructure
• Experience with graph optimization, IR transformations or lowering
• Ability to reason across compiler decisions and hardware behavior

Experience with PyTorch compilation, Triton, GPUs, AI accelerators, memory optimization or hardware/software co-design would be particularly valuable.

This is an opportunity to shape a compiler while both the software stack and target architecture are still evolving.