Graph Compiler Performance Engineer for AI Pipelines

Meta; Menlo Park (CA); On-site; USD 184,000 - 257,000; Full time

Job summary

Meta seeks a Compiler Engineer focused on Graph Compiler Performance Optimization within the MTIA Software team. You will shape graph-level compiler passes for PyTorch Inductor/FX IR, profiling models to remove bottlenecks, and extending fusion and memory optimizations across MTIA hardware generations.

You will collaborate with AI researchers and hardware teams, ensuring scalable, portable compiler strategies and rapid silicon bring-up. Strong C/C++ and Python skills required.

Qualifications

• Experience with C/C++ and Python programming.
• Experience in compiler development and optimizing ML models on hardware.
• Understanding of graph execution and how compiler transforms affect performance.
• Bachelor's degree in CS/CE or equivalent practical experience.

Responsibilities

• Design, implement, and validate graph-level compiler optimization passes targeting performance within the PyTorch Inductor / FX IR compilation pipeline for MTIA.
• Profile and analyze deep learning models to identify graph-level performance bottlenecks and develop compiler solutions.
• Develop and extend automatic fusion strategies to unlock peak hardware utilization across MTIA chip generations.
• Implement memory optimizations to reduce latency and improve bandwidth utilization.
• Build and improve performance analysis tooling to accelerate optimization iteration cycles.
• Collaborate with hardware design teams on hardware-software co-design for new silicon capabilities.
• Ensure compiler optimizations are portable and scalable across MTIA chip generations.

Skills

C/C++

Python

Compiler development

DL models

Education

Bachelor's in CS/CE

Tools

PyTorch internals

Job description

Meta seeks a Compiler Engineer focused on Graph Compiler Performance Optimization within the MTIA Software team. You will shape graph-level compiler passes for PyTorch Inductor/FX IR, profiling models to remove bottlenecks, and extending fusion and memory optimizations across MTIA hardware generations.

You will collaborate with AI researchers and hardware teams, ensuring scalable, portable compiler strategies and rapid silicon bring-up. Strong C/C++ and Python skills required.