Senior Graph Optimization Engineer

Lemurian Labs Inc.; Santa Clara (CA); On-site; USD 180,000 - 230,000; Full time

Benefits offered by this job

Equity

Medical benefits

Retirement plan

Wellness benefits

Job summary

Lemurian Labs is building a hardware-agnostic AI compiler stack and seeks a Graph Optimization Compiler Engineer to own the middle tier, transforming high-level graphs into efficient code. You will influence fusion, layout, and IR design that directly impacts performance across diverse hardware targets.

We value engineers who think in data-flow graphs and optimization passes, able to measurably improve throughput and latency while collaborating with front-end and code-generation teams.

Qualifications

• BS degree in CS/CE or equivalent practical experience.
• 4+ years of compiler experience focused on IR design or optimization passes.
• Deep knowledge of graph-level optimization: fusion, tiling, layout transformations.
• 4+ years of C/C++ experience.
• Strong written and verbal communication; ability to write clear technical docs.

Responsibilities

• Design, develop, and maintain the graph optimization layer of our heterogeneous AI compiler.
• Implement and extend graph-level transformation passes including fusion, layout propagation, dead code elimination, constant folding, and algebraic simplification.
• Define and evolve our intermediate representation to support new optimization opportunities.
• Analyze performance data to identify gaps and drive throughput and latency improvements.
• Collaborate with front end and code generation teams to ensure clean IR interfaces and pipelines.
• Prototype new optimization strategies in response to advances in models and hardware.

Skills

Graph optimization

C/C++

Compiler design

Documentation

Education

BS degree in Computer Science or Computer Engineering

Master's or PhD in Computer Science or Engineering

Tools

MLIR

XLA

Job description

Lemurian Labs is building a hardware-agnostic AI compiler stack and seeks a Graph Optimization Compiler Engineer to own the middle tier, transforming high-level graphs into efficient code. You will influence fusion, layout, and IR design that directly impacts performance across diverse hardware targets.

We value engineers who think in data-flow graphs and optimization passes, able to measurably improve throughput and latency while collaborating with front-end and code-generation teams.