Lead AI Graph Compiler Engineer

EnCharge AI; United States; Remote; USD 190,000 - 255,000; Full time

Job summary

EnCharge AI seeks an AI Compiler Engineer to spearhead graph compiler optimizations for AI/ML workloads on Inference Accelerators. You will collaborate with hardware architects and researchers to improve model deployment efficiency and reduce latency across edge-to-cloud systems.

The role requires 3+ years in compiler development, strong MLIR/Torch-FX experience, and deep knowledge of GPUs/TPUs/ASICs with fusion, quantization, and tiling. Leadership is a plus.

Qualifications

• 3+ years in compiler development focusing on AI/ML graphs.
• Proficiency with MLIR and Torch-FX frameworks.
• Strong hardware knowledge of GPUs/TPUs/ASICs and optimization techniques.

Responsibilities

• Architect, design, and implement optimizations for AI model execution on graph compilers to improve performance, reduce latency, and maximize hardware utilization.
• Work closely with ML researchers, hardware engineers, and software developers to design and deploy AI models, understanding and addressing hardware-specific challenges.
• Work on performance optimizations for neural network models, such as layer fusion, operator fusion, and graph-level transformations.
• Develop compiler optimizations and passes that convert high-level AI models (e.g., from TensorFlow, PyTorch) into intermediate representations (IR).
• Implement parsing, semantic analysis, and IR generation for deep learning frameworks.
• Research and integrate the latest advancements in compiler design, ML model optimizations, and hardware acceleration into graph compilers.
• Provide leadership, mentorship, and technical guidance to a team of engineers focused on graph compiler optimizations.

Skills

AI graph compilers

MLIR

Torch-FX

C++

Python

Hardware optimization

Team leadership

Education

Bachelor's or Master's in CS/EE

PhD preferred

Tools

TensorFlow

PyTorch

Job description

EnCharge AI seeks an AI Compiler Engineer to spearhead graph compiler optimizations for AI/ML workloads on Inference Accelerators. You will collaborate with hardware architects and researchers to improve model deployment efficiency and reduce latency across edge-to-cloud systems.

The role requires 3+ years in compiler development, strong MLIR/Torch-FX experience, and deep knowledge of GPUs/TPUs/ASICs with fusion, quantization, and tiling. Leadership is a plus.