GPU Power Management & RTL Design Engineer - Apple Silicon

The Briefed; Austin (TX); On-site; USD 120,000 - 170,000; Full time

Job summary

Apple in Austin is seeking a senior RTL engineer to design and optimize RTL for GPU power management and SoC interface logic. You will collaborate with Platform Architecture, Software, Design Verification, and Physical Design teams to deliver RTL and specifications, integrate IP, and drive performance, power, and area goals across multi-site teams.

The role requires a BS in EE, CE, or ECE, strong Verilog/SystemVerilog RTL experience, and scripting skills.

Qualifications

• BS in EE, CE, or ECE.
• Experience in logic optimization, synthesis, timing analysis, floor-planning, power intent descriptions, and clock domain crossings.
• Experience writing RTL in Verilog and/or SystemVerilog; experience with logic simulation and debug.

Responsibilities

• Deliver RTL design collateral, including RTL, to Physical Design teams.
• Assess and integrate IP from other Apple teams.
• Close timing, power, area, and lint by optimizing RTL and constraints.
• Drive performance, power, area, and functional goals.
• Provide schedules to IP teams and management.
• Collaborate with IP teams across multiple sites.

Skills

RTL design

Verilog

SystemVerilog

Logic optimization

Synthesis

Timing analysis

Floor-planning

Power integrity

Clock domain crossings

IP integration

Scripting languages

Education

BS in EE, CE, or ECE

Job description

As part of Apple’s Silicon Technologies group, you would help design and manufacture the next-generation, high-performance, power-efficient processor system-on-chip (SoC) that powers Apple’s devices. On the mobile GPU design team, you would work with Platform Architecture, Software, Design Verification, and Physical Design teams to deliver RTL and specifications for GPU power management and SoC interface logic. You would also integrate IP from other teams to enable complete security, debug, and power management solutions. The goal is hardware that performs well and delivers long battery life.

Key responsibilities

• Deliver high-quality design collateral, including RTL, to Physical Design teams.
• Assess and integrate IP from other Apple teams.
• Close timing, power, area, and lint by optimizing RTL and constraints.
• Drive performance, power, area, and functional goals.
• Provide schedules to IP teams and management.
• Collaborate with IP teams across multiple sites.

Experience and education required

• BS in EE, CE, or ECE.
• Experience in one or more of: logic optimization, synthesis, timing analysis, floor-planning, power intent descriptions, and clock domain crossings.
• Experience writing RTL in Verilog and/or SystemVerilog.
• Experience with logic simulation and debug.
• A specific number of years of experience is not stated.

Preferred

• Ability to write one or more scripting languages.
• Experience in graphics hardware design.
• Experience in power management for large designs such as CPUs, GPUs, or SoCs.

Technical skills

• RTL design in Verilog and SystemVerilog
• Logic optimization, synthesis, and timing analysis
• Floor-planning and power intent descriptions
• Clock domain crossings
• Logic simulation and debug
• GPU power management and SoC interface logic
• IP integration (security, debug, power management)
• Scripting languages (preferred)

Soft skills

• Attention to detail
• Creative problem solving for complex challenges
• Cross-team and multi-site collaboration
• Scheduling and communication with IP teams and management