Formal Verification Engineer — Build Next-Gen Silicon (Equity)

NVIDIA; Santa Clara (CA); Presencial; USD 100.000 - 190.000; Jornada completa

Descripción de la vacante

NVIDIA in Santa Clara, CA is seeking a Formal Verification Engineer to join our team responsible for verifying RTL units of next generation chips. You will own the verification plan, build test environments, and apply advanced formal techniques to ensure correctness and reliability.

The ideal candidate has a CS/CE/EE/Math degree, strong analytical ability, experience with Verilog/SystemVerilog and formal tools (Jasper, IFV, SMV, SPIN), and excellent communication to collaborate with design

Formación

• BS or MS in CS/CE/EE/Math or equivalent experience.
• Strong analytical skills.
• Knowledge/Experience in formal verification techniques.
• Strong knowledge of architectures of CPU/GPU designs and digital logic.
• Understanding of abstraction techniques for effective verification.
• Hands-on experience with HDLs such as Verilog / System Verilog.
• Ability to understand RTL quickly.
• Understanding of temporal logic assertions.
• Preferable experience with Formal Verification Tools (eg. Jasper, IFV, SMV, SPIN)
• Excellent communication skills with ability to work with team members and collaborate effectively.

Responsabilidades

• Developing comprehensive FV testplan documents.
• Identifying key behaviors for verification of DUT and creating a verification plan.
• Developing verification environment including environment assumptions, assertions and cover properties in context of the verification plan.
• Applying various FV techniques to proof correctness of digital designs.
• Debugging RTL to identify failure scenarios.
• Developing scripts to automate the verification process.
• Review formal setups and proofs with design and verification teams.

Conocimientos

Formal verification

HDL Verilog/SystemVerilog

Digital logic

CPU/GPU architectures

Temporal logic

Formal verification tools (Jasper, IFV

SPIN

Communication skills

Educación

BS/MS in CS/CE/EE/Math

Herramientas

Jasper

IFV

SMV

SPIN

Descripción del empleo

NVIDIA in Santa Clara, CA is seeking a Formal Verification Engineer to join our team responsible for verifying RTL units of next generation chips. You will own the verification plan, build test environments, and apply advanced formal techniques to ensure correctness and reliability.

The ideal candidate has a CS/CE/EE/Math degree, strong analytical ability, experience with Verilog/SystemVerilog and formal tools (Jasper, IFV, SMV, SPIN), and excellent communication to collaborate with design