Member of Technical Staff - Design Verification

Architect Labs; Palo Alto (CA); On-site; USD 210,000 - 320,000; Full time

Benefits offered by this job

Competitive salary

Meaningful equity stake

Autonomy and visible impact

Cutting-edge AI and silicon challenges

Job summary

Architect Labs is seeking a Founding Member of the Technical Staff to lead the Design Verification efforts for AI-driven design automation. You will own the verification strategy for AI-generated designs taping out on leading foundries and collaborate across hardware and AI teams.

This role combines hands-on DV with leadership, enabling scalable validation across IPs, emulation, and FPGA prototyping, in a fast-paced startup environment in Palo Alto.

Qualifications

• Degree in Electrical Engineering, Computer Engineering, or closely related field.
• 5+ years tapeout experience on advanced-node designs; 10+ preferred.
• DV expertise in verification, emulation, and IP/SoC validation platforms.
• Strong coding in SystemVerilog, UVM, C/C++, Python preferred.
• Hands-on with ARM AMBA, CPU subsystems, memory controllers, NoC.

Responsibilities

• Review AI-driven test plans and validation strategies for internal and external SoC projects.
• Provide domain expertise to AI/ML teams for architectural and microarchitectural checks, validation modularity, and interfaces.
• Define and coordinate validation and integration flows across multiple IPs with checkpoints and collateral handoffs.
• Collaborate with architecture, design, and AI/ML leads to generate simulation- and emulation-ready collateral.
• Track trends in semiconductor verification and AI-driven design automation to keep methodology cutting-edge.

Skills

SystemVerilog

UVM

Python

C/C++

Problem-solving

Leadership

Education

Bachelor’s/Master’s/PhD in Electrical Engineering or related field

Tools

Xilinx Vivado/Vitis

Emulation Tools

FPGA Prototyping

Simulation

Job description

What You’ll Do

As a Founding Member of the Technical Staff on the Design Verification team at Architect, you'll own the verification strategy behind AI-generated designs taping out on leading foundries. You'll work at the intersection of rigorous hardware verification and AI-driven design automation.

• Review AI-driven test plan, and validation strategy for internal and external SoC projects.
• Provide domain-specific expertise to our AI/ML teams, including architectural and microarchitectural checks, validation modularity, checkers, coverage models, and interface protocols — helping encode DV best practices into our AI-driven flows.
• Independently define, drive, and coordinate validation, verification, and integration flows across multiple IPs, including checkpoints and collateral handoffs.
• Collaborate with architecture, design, and AI/ML leads to generate simulation- and emulation-ready collateral that scales across projects.
• Track emerging trends in semiconductor verification and AI-driven design automation to keep our methodology cutting-edge in quality, scalability, and throughput.

What We’d Like to See

Qualifications & Skills:

• Degree: Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or a closely related field.
• Tapeout Experience: 5+ years (10+ preferred) working on advanced-node tapeouts at top chip companies or fast-moving silicon startups. End-to-end silicon delivery is a strong plus.
• Verification Expertise: Deep expertise in verification/validation, emulation, and architectural and system-level verification of industry-standard IPs. Proven track record defining microarchitectural checkers and monitors, modeling IP and SoC validation platforms, and developing modular, reusable validation collateral.
• Coding: Strong skills in SystemVerilog, UVM, and C/C++ for test environments. Python strongly preferred.
• Subsystem Depth: Hands-on verification experience in at least one of the following areas:
• ARM/AMBA protocols (APB, AHB, AXI, and ideally ACE for coherent CPU interfaces)
• CPU subsystems — boot, interrupts, debug, coherency
• Memory controllers and PHY — LPDDR/DDR interfaces, controller-level verification
• On-chip interconnect / NoC — routing, arbitration, QoS, bandwidth
• NPU / ML accelerator cores — datapath, scratchpad memory, DMA engines
• Security IPs and/or working with secure enclaves
• Methodology: Hands-on experience with simulation and emulation flows and methodologies. Experience mapping IP and SoC designs to FPGA prototypes for fast functional verification.
• Execution: Excellent problem-solving, collaboration, and communication skills with strong attention to detail. Ability to work independently and drive cross-functional alignment.
• Leadership: Ability and desire to lead the DV function over time as the team scales.

Bonus:

• SoC-level DV experience – bringing up full systems with memory controller + PHY + CPU connectivity, validating top-level integration.
• Deep experience with AMBA protocols, specifically ACE for coherent CPU-memory access.
• FPGA prototyping experience (ideally Xilinx Vivado/Vitis).
• Verification experience spanning multiple of: interconnects, CPU subsystems, ARM AMBA, memory controllers, NPUs.
• Tapeout experience at frontier AI chip startups (MatX, Groq, Cerebras, d-Matrix, etc.) or tier-1 silicon companies (Apple, NVIDIA, Google, Qualcomm, Broadcom, AMD).

What We Offer

• Competitive salary and meaningful equity stake
• Fast-paced startup with autonomy and visible impact
• Cutting-edge challenges at the intersection of AI and silicon design