Front End Design Verification Engineer

Tenstorrent; Santa Clara (CA); Remote; USD 100,000 - 500,000; Full time

Job summary

Tenstorrent is seeking a Front End Design Verification Engineer to verify the fetch unit for our high-performance RISC-V CPU cores. You will partner with CPU architects and RTL designers to develop verification strategies, create tests, and debug failures across workloads.

We welcome candidates at various experience levels, with remote work available from North America or Spain. Compensation ranges widely, reflecting base and variable components, and offers are aligned with experience level.

Qualifications

• 6+ years of design verification for CPUs, SoCs, ASICs, or other complex digital designs.
• Strong experience with SystemVerilog and UVM, including constrained-random testing, assertions, functional coverage, and testbench development.
• Solid understanding of CPU architecture, with familiarity in pipelines, instruction fetch/decode, branch prediction, speculative execution, or out-of-order execution.
• Experience debugging RTL and simulation failures using waveforms and standard simulation/debug tools.
• Strong programming skills in C/C++ and/or Python, with the ability to collaborate across architecture, RTL, DV, and software teams.

Responsibilities

• Verify the fetch unit and front-end for high-performance RISC-V CPU cores.
• Develop verification strategies, tests, and debug complex failures to ensure correctness across workloads and corner cases.
• Collaborate with CPU architects and RTL designers to validate instructions fetch, decode, and dispatch.

Skills

SystemVerilog

UVM

C/C++

Python

CPU architecture

Debugging RTL

Tools

Waveform tools

Simulation environment

Job description

Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.

Tenstorrent is looking for a Front End Design Verification Engineer to help verify the fetch unit for our next generation of high-performance RISC-V CPU cores. You’ll work on the logic responsible for keeping the processor fed with the right instructions at the right time—from instruction fetch and prediction through decode and dispatch. You’ll partner closely with CPU architects and RTL designers to develop verification strategies, create sophisticated tests, debug complex failures, and ensure the front end behaves correctly across a wide range of workloads and corner cases. This is an opportunity to make a direct impact on the performance and correctness of a high performance out-of-order CPU.

This role isremote, based out of North America or Spain.

We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.

Who You Are

• A hands-on verification engineer who enjoys digging into complex processor behavior and finding subtle bugs.
• Comfortable working with CPU front-end concepts such as instruction fetch, branch prediction, instruction decode, queues, and dispatch.
• A strong problem solver who can move between specifications, RTL, simulations, and waveforms to identify root causes.
• Collaborative and proactive, with the ability to work closely with architects, RTL designers, and other DV engineers.
• Curious about high-performance CPUs and excited to learn how microarchitectural decisions impact real-world processor performance.

What We Need

• 6+ years of experience in design verification for CPUs, SoCs, ASICs, or other complex digital designs.
• Strong experience with SystemVerilog and UVM, including constrained-random testing, assertions, functional coverage, and testbench development.
• Solid understanding of CPU architecture, with familiarity in areas such as pipelines, instruction fetch/decode, branch prediction, speculative execution, or out-of-order execution.
• Experience debugging RTL and simulation failures using waveforms and standard simulation/debug tools.
• Strong programming skills in C/C++ and/or Python, with the ability to collaborate effectively across architecture, RTL, DV, and software teams.

What You Will Learn

• Gain deep experience verifying the front end of a high-performance, out-of-order RISC-V CPU.
• Learn how instruction fetch, branch prediction, decode, and dispatch work together to keep a modern CPU pipeline running efficiently.
• Develop expertise in verifying speculative execution and the complex corner cases created by branches, redirects, exceptions, and pipeline flushes.
• Learn how architectural specifications and microarchitectural designs translate into RTL and comprehensive verification environments.
• Work alongside CPU architects and RTL engineers on processors designed for demanding AI, HPC, and high-performance computing workloads.

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.

This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.