Front-End CAD Engineer for ASIC/SoC EDA Tools

Ericsson GmbH; Austin, Northern (TX, KY); Hybrid; USD 178,000 - 195,000; Full time

Benefits offered by this job

Health benefits

401(k) with company match

Bonus opportunity

Paid time off

Job summary

Ericsson Inc. in Austin, TX is seeking a Developer (Front End Infrastructure CAD Engineer) to develop, deploy, and support advanced EDA tools for ASIC/SoC/FPGA IP design and verification.

The role emphasizes collaboration with tool vendors, foundries and third-party IP providers, and requires strong scripting along with RTL/HDL skills. Hybrid work policy within commuting distance, with responsibilities spanning modeling, RTL design, verification, CAD stream improvements, and CI automation.

Qualifications

• Bachelor’s (or foreign equivalent) in Electrical/Electronics Engineering or related field with 5 years of hardware/software development experience.
• Master’s (or foreign equivalent) in Electrical/Electronics Engineering or related field with 2 years of hardware/software development experience.

Responsibilities

• Develop, deploy and support complex EDA software tools for ASIC/SoC/FPGA IP design & verification.
• Collaborate with EDA tool vendors, foundries and IP vendors to troubleshoot and optimize design flows.

Skills

Python scripting

Verilog

SystemVerilog

UVM

RTL design

C/C++

Education

Bachelors in EE

Masters in EE

Tools

Jenkins

EDA tools

Linux

Job description

Ericsson Inc. in Austin, TX is seeking a Developer (Front End Infrastructure CAD Engineer) to develop, deploy, and support advanced EDA tools for ASIC/SoC/FPGA IP design and verification.

The role emphasizes collaboration with tool vendors, foundries and third-party IP providers, and requires strong scripting along with RTL/HDL skills. Hybrid work policy within commuting distance, with responsibilities spanning modeling, RTL design, verification, CAD stream improvements, and CI automation.