Engineer|5287 Engineer|5287

ALTEN; San Diego (CA); On-site; USD 90,000 - 120,000; Full time

Job summary

ALTEN is seeking a CAD Development Engineer in San Diego, CA to join our Technologies Inc Global CAD team. The role involves developing RTL2GDS implementation tools and supporting CAD tools for synthesis, floor planning, and place & route for cutting-edge product designs. Candidates should have 2+ years in CAD flow development, familiarity with EDA tools, and skills in Tcl and Python. A Bachelor's degree in Computer Engineering, Computer Science, or Electrical Engineering is required. Join us to help build the latest tools for complex chip designs.

Qualifications

• Hands-on expertise in developing and maintaining CAD tools for digital design.
• Knowledge of industry EDA tools and PPA optimization techniques.
• Strong logical and creative problem-solving skills.
• Excellent interpersonal skills and ability to work independently.
• Highly motivated with excellent team spirit.

Responsibilities

• Develop and support CAD tools and flows for Synthesis, Floorplan, and Place & Route.
• Debug issues for design closure in advanced process nodes.
• Regression and test analysis of QoR results.
• Collaborate with design and CAD teams.
• Interface with EDA vendors for production-ready tools.

Skills

Synthesis

Floorplan

Place and Route

Static Timing analysis

IR drop analysis

Physical verification

Logic verification

Tcl

PERL

Python

Education

Bachelor's in Computer Engineering

Bachelor's in Computer Science

Bachelor's in Electrical Engineering

Tools

Synopsys Tools

Cadence Tools

Mentor Graphics Tools

Ansys Tools

Job description

Join our Technologies Inc Global CAD team delivering SoC design CAD Tools for leading-edge products. The position requires experienced CAD development Engineer to develop RTL2GDS implementation tools and flows for new methodologies of PPA and Sign-off in cutting edge process nodes.

CAD team at QCOM is looking for long term Temp staffing for driving Tools and Flows for upcoming Snapdragon products.

Keywords & Tools

• Synthesis, Floorplan, Place and Route, Static Timing analysis, IR drop analysis, Physical verification and Logic verification.
• The Tools and flows are based on EDA vendors Synopsys, Cadence, Mentor, Ansys who deliver EDA tools for Chip design.
• Synopsys : Fusion Compiler, Design compiler (DC), Formality, Tetramax, PrimeTime, STAR-RC, IC validator
• Cadence : Genus, Innovus, Conformal, Tempus, Voltus
• Mentor : Aprisa, AtopTech, Tessent, Calibre
• Ansys: redhawk, Totem
• These engineers may have worked at these vendors, or at chip companies. If they have worked at ANY EDA vendor, that is a BIG PLUS.
• At chip companies, engineers titles will be CAD engineer, PD engineer, Synthesis engineer. They are NOT CAD engineers but they can still be trained by CAD team, depending upon their interest in LEARNING the deep-down knowledge of tools and not just push buttons. This is a very high value skill which CAD engineers build.
• We also have work in adjacent areas. If a candidate has done Spice simulations, IP design, memory design we can check them as well.
• For CAD, it is good idea to have some automation skills. Tcl, PERL, Python are good languages to know and help.

Overall our team builds tools and flow for the most complex chips, in most advanced technologies. We welcome the engineers to learn and build latest tool platforms.

Responsibilities

• Develop and support CAD tools and flows for Synthesis, Floorplan, Place and Route and ECO.
• Debug issues and provide solutions for design closure in advanced process nods.
• Regression, Test, analysis of QoR results and develop recipe for PPA and runtime/compute optimization.
• Collaboration with design teams, CAD teams.
• Interfacing with EDA vendors to enable production-ready tool sets that satisfy projects requirement.

Minimum Qualification Requirements

• Hands on expertise in developing and maintaining CAD tool for digital design.
• Knowledge of Industry EDA tools and PPA optimization techniques.
• Strong logical and creative problem-solving skills with excellent analytical and debugging skills.
• Excellent interpersonal and analytical skills with the ability to work independently.
• Highly motivated, excellent team spirit, product and customer oriented.
• 2-4 years experience.

Preferred Qualifications

• 3+ years CAD flow development for ASIC design, floorplan, place and route and related work experience.
• 2+ years experience in advanced process technology.
• 2+ years experience with EDA vendor tools.
• 2+ years hands‑on experience with Tcl and Python languages.

Education Qualifications

Required: Bachelors Computer Engineering and/or Computer Science and/or Electrical Engineering with courses on VLSI and/or CAD tools.