Front-End ASIC Design Engineer: RTL & Verilog

University of Southern California; Arlington (VA); On-site; USD 115,000 - 140,000; Full time

Job summary

University of Southern California’s Information Sciences Institute in Arlington, VA is hiring an ASIC Research Engineer for front-end digital design. You will design and verify RTL models of CPUs, memories and accelerators using Verilog, SystemVerilog or VHDL, and collaborate with MOSIS 2.0 service and third-party IP cores.

The role requires a degree in Computer or Electrical Engineering with 3+ years experience (or a Master’s) and strong Linux, scripting, and revision control skills.

Qualifications

• Bachelor’s degree in Computer or Electrical Engineering; >3 years experience or Master’s degree
• RTL/Verilog/SystemVerilog/VHDL RTL design experience
• Solid understanding of computer architecture and microarchitecture
• Experience with Linux and scripting; revision control tools

Responsibilities

• Design and verify RTL models of CPUs, memories and accelerators.
• Collaborate with MOSIS 2.0 service and integrate third-party IP cores.
• Engage with sponsor programs (DARPA, IARPA, CHIPS Act) and work in a fast-moving research setting.

Skills

RTL design

Verilog

SystemVerilog

VHDL

Computer architecture

Microarchitecture

Linux

Scripting

Revision control

Education

Bachelor’s degree in Computer/Electrical Engineering

Master’s degree

Tools

EDA tools

FPGAs

Job description

University of Southern California’s Information Sciences Institute in Arlington, VA is hiring an ASIC Research Engineer for front-end digital design. You will design and verify RTL models of CPUs, memories and accelerators using Verilog, SystemVerilog or VHDL, and collaborate with MOSIS 2.0 service and third-party IP cores.

The role requires a degree in Computer or Electrical Engineering with 3+ years experience (or a Master’s) and strong Linux, scripting, and revision control skills.