Senior ASIC Front-end RTL Design Engineer – Research

Aimlroles; Virginia; Presencial; USD 140.000 - 170.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Education benefits for family

Medical and retirement benefits

Hybrid work flexibility

Descripción de la vacante

USC Information Sciences Institute (ISI) in Arlington, VA, seeks a Senior ASIC Research Engineer – Front-end Digital Design to design and verify RTL models of CPUs, memories, and accelerators for national importance projects. You will work with a cutting-edge team and may collaborate with MOSIS 2.0, integrate third-party IP cores, and engage with DARPA/IARPA and CHIPS Act sponsors.

The role is based in ISI's Arlington, VA office, offering a collaborative university setting with learning and

Formación

• Degree in Computer Engineering, Electrical Engineering or related field.
• Master’s degree with >5 years of experience.
• Demonstrated excellence creating digital designs with Verilog, SystemVerilog or VHDL RTL.
• Solid understanding of computer architecture and microarchitecture.
• Demonstrated skills with EDA tools (logic synthesis, timing), scripting, revision control.

Responsabilidades

• Design RTL models of CPUs, memories, and accelerators.
• Verify RTL designs and ensure correctness.
• Collaborate with MOSIS 2.0 service and integrate third-party IP cores.
• Engage with sponsors such as DARPA, IARPA and CHIPS Act.

Conocimientos

Verilog

SystemVerilog

VHDL RTL

Computer Architecture

EDA Tools

Scripting

Revision Control

Linux

Educación

Master’s degree in Computer Engineering / Electrical Engineering

Bachelor’s degree in Computer Engineering / Electrical Engineering

Herramientas

Docker

MOSIS 2.0

Descripción del empleo

USC Information Sciences Institute (ISI) in Arlington, VA, seeks a Senior ASIC Research Engineer – Front-end Digital Design to design and verify RTL models of CPUs, memories, and accelerators for national importance projects. You will work with a cutting-edge team and may collaborate with MOSIS 2.0, integrate third-party IP cores, and engage with DARPA/IARPA and CHIPS Act sponsors.

The role is based in ISI's Arlington, VA office, offering a collaborative university setting with learning and