ASIC Front-End RTL Engineer for Digital Design

Aimlroles; Virginia; On-site; USD 115,000 - 140,000; Full time

Benefits offered by this job

Free university education for you and

Education benefits for you and your/

Great benefits – medical to matched退休

Job summary

USC Information Sciences Institute in Arlington, VA, is seeking an ASIC Research Engineer to design and verify RTL models for CPUs, memories, and accelerators used in communications, signal processing, and security applications.

You will collaborate with the MOSIS 2.0 service, integrate IP cores, and gain experience with top sponsors like DARPA, IARPA, and CHIPS Act in a fast-paced research environment.

Qualifications

• Degree in Computer Engineering, Electrical Engineering or related field.
• Bachelor’s degree with >3 years of experience, or Master’s degree.
• Demonstrated excellence creating digital designs with Verilog, SystemVerilog, or VHDL RTL.
• Solid understanding of computer architecture and microarchitecture.
• Demonstrated skills with EDA tools, scripting, revision control.

Responsibilities

• Design and verify RTL models of CPUs, memories and accelerators.
• Collaborate with MOSIS 2.0 service and integrate third‑party IP cores.
• Work on RTL verification and timing modeling.
• Engage with sponsors and work in a fast-moving research setting.

Skills

RTL design

Computer architecture

EDA tools & scripting

Linux

Communication

Education

Bachelor’s degree in Computer/Electrical Engineering or related field

Master’s degree (preferred)

Tools

FPGA design

Docker

TensorFlow

PyTorch

HuggingFace

Job description

USC Information Sciences Institute in Arlington, VA, is seeking an ASIC Research Engineer to design and verify RTL models for CPUs, memories, and accelerators used in communications, signal processing, and security applications.

You will collaborate with the MOSIS 2.0 service, integrate IP cores, and gain experience with top sponsors like DARPA, IARPA, and CHIPS Act in a fast-paced research environment.