FPGA Design Engineer: Pre-Silicon Validation & PCIe

Normal Computing Corp.; Palo Alto (CA); On-site; USD 120,000 - 190,000; Full time

Job summary

Normal Computing is an applied AI company building foundational hardware and software for the semiconductor industry. We seek an FPGA Design Engineer to own the bridge between RTL and physical silicon, bringing ASIC designs to life on FPGA platforms for pre-silicon validation and early software development.

You will manage FPGA platform selection, implement complex RTL on FPGA targets, and collaborate with silicon, EDA, and research teams to build the test infrastructure and software stack

Qualifications

• Proven industry experience taking FPGA designs from RTL through timing closure to validated hardware.
• Expert-level SystemVerilog and/or VHDL for synthesis, with deep proficiency in Xilinx Vivado.
• Hands-on experience implementing and debugging PCIe, plus AXI/AHB, SPI, UART, JTAG, and other interfaces.
• Strong Python for automation, test, and build tooling.
• Strong board-level bring-up and lab debugging skills on real hardware.
• Startup mindset: you work independently across HW, SW, and physics.

Responsibilities

• FPGA Platform Ownership: lead selection, procurement, and bring-up of FPGA prototyping platforms for pre-silicon RTL validation and software development.
• RTL Implementation: adapt ASIC RTL onto FPGA targets, including multi-clock-domain architectures and timing closure.
• IP Integration: integrate in-house designs with vendor IP; expert on AMD/Xilinx ecosystem.
• High-Speed Interfaces: design and validate high-speed I/O with a focus on PCIe in standard servers.
• Post-Silicon Validation: build FPGA-based testers for silicon bring-up and characterization.
• Hardware-Software Stack: develop the software layer around hardware (Python/C++).
• Lab Debug: root-cause timing and functional issues using ILA/Vivado Analyzer and lab tools.

Skills

SystemVerilog/VHDL

Python

Lab debugging

PCIe

Xilinx Vivado

Tools

Vivado IP Integrator

HAPS / VCU118

Job description

Normal Computing is an applied AI company building foundational hardware and software for the semiconductor industry. We seek an FPGA Design Engineer to own the bridge between RTL and physical silicon, bringing ASIC designs to life on FPGA platforms for pre-silicon validation and early software development.

You will manage FPGA platform selection, implement complex RTL on FPGA targets, and collaborate with silicon, EDA, and research teams to build the test infrastructure and software stack