FPGA Engineer

Owen Daniels; Arizona; On-site; USD 110,000 - 160,000; Full time

Benefits offered by this job

3 weeks vacation

1 week personal

1 week sick leave

10 holidays (T4 Staff level)

medical/dental/vision

Job summary

Owen Daniels seeks a Senior FPGA Engineer to lead the design, development, and debug of FPGA SoC systems for satellite communications. You will manage IP integration through RTL and firmware, working across hardware and software teams in a fast-paced space tech environment.

The ideal candidate has 5+ years in FPGA/SoC roles, strong experience with Xilinx/Vivado and Quartus, and proficiency in AMBA interfaces and network protocols. Arizona-based, full-time on-site role with competitive benefits.

Qualifications

• BS in EE, CS, or equivalent; 5+ years' industry experience.
• Hands-on with Xilinx Vivado and Altera Quartus; simulation in ModelSim/QuestaSim.
• SoC debug experience with AMBA AXI/APB interfaces and AXI-Stream IP.
• RTL simulation, STA, and SDC experience.
• Familiarity with GbE/PCIe/other gigabit transceiver protocols.
• Network protocol knowledge (Ethernet, IPv4/IPv6, TCP/UDP); eCPRI/VITA 49.2 is a plus.
• Embedded C/C++, microcontrollers, Git; bonus: Embedded Linux and PCB debug.

Responsibilities

• Lead design, development and debug of FPGA SoC systems for satellite comms.
• From IP integration through high-performance RTL and firmware.
• Collaborate across hardware, software and systems teams.

Skills

SoC Debug

AXI/APB interfaces

RTL simulation

Static Timing Analysis

Network protocols (Ethernet, TCP/IP)

Embedded C/C++

Firmware development

Education

BS in EE/CS or equivalent

Tools

Xilinx Vivado

Altera Quartus

ModelSim/QuestaSim

Git

Yocto/U-Boot/DeviceTree

Schematic capture/PCB debug

Job description

Company Overview and Role:

A global leader in Satellite and Space technology is hiring a Senior FPGA Engineer to join their Platforms and FPGA SoC Group. You'll lead the design, development, and debug of complex FPGA SoC systems for satellite communications — from IP integration through high-performance RTL and firmware.

What you'll bring:

• BS in EE, CS, or equivalent; 5+ years' industry experience
• Strong hands-on with Xilinx Vivado and Altera Quartus; simulation in ModelSim/QuestaSim
• SoC debug experience with AMBA AXI/APB interfaces; fmax-optimized, pipelined AXI-Stream IP
• RTL simulation, Static Timing Analysis, and SDC
• At least one Gigabit transceiver protocol (PCIe, Interlaken, USB SuperSpeed, 1000BASE-X/SGMII, 10/40/100GBASE-R)
• Network protocol experience (Ethernet L1/L2/L3, IPv4/IPv6, TCP/UDP); VITA 49.2/DIFI or eCPRI a strong plus
• Embedded C/C++, microcontrollers, Git
• Bonus: Embedded Linux (Kernel/Yocto/U-Boot/DeviceTree), schematic capture/PCB debug
• Industry background in Satellite, Space, or Wireless preferred

Benefits:

3 weeks vacation, 1 week personal, 1 week sick leave, 10 holidays (T4 Staff level), full medical/dental/vision, and more.