Senior FPGA Engineer for High-Performance Networking

GCS Recruitment; Oregon (WI); On-site; USD 110,000 - 160,000; Full time

Job summary

GCS Recruitment is seeking an experienced FPGA Engineer to design and develop FPGA solutions for a next-generation satellite communication system. You will own FPGA bitstreams, collaborate with system architects, and drive the full development lifecycle from RTL design to production release.

The role requires 7+ years of hands-on FPGA design, expertise in Verilog HDL, experience with AMD Xilinx Versal ACAP and Microchip IGLOO2, and proficiency with Vivado and Libero SoC.

Qualifications

• Bachelor's degree in Electrical/Computer Engineering or related field.
• 7+ years of hands-on FPGA design experience.
• Strong Verilog HDL for RTL design and verification.
• Experience with AMD Xilinx Versal ACAP and Microchip IGLOO2 platforms.

Responsibilities

• Own the development and delivery of one or more FPGA bitstreams.
• Design, develop, and implement complex FPGA architectures using Verilog HDL.
• Lead FPGA development across the full lifecycle: microarchitecture, RTL, timing, verification, lab validation.
• Collaborate with system architects, hardware, firmware and software teams to implement FPGA solutions.
• Develop testbenches, perform synthesis, place & route, and timing analysis.
• Provide hardware bring-up, debugging, and production deployment support.

Skills

Verilog HDL

SystemVerilog

Python scripting

Timing closure

Education

Bachelor's degree in Electrical / Computer Engineering or related field

Tools

Xilinx Vivado

Libero SoC

Vivado Simulator

ModelSim

VCS

Job description

GCS Recruitment is seeking an experienced FPGA Engineer to design and develop FPGA solutions for a next-generation satellite communication system. You will own FPGA bitstreams, collaborate with system architects, and drive the full development lifecycle from RTL design to production release.

The role requires 7+ years of hands-on FPGA design, expertise in Verilog HDL, experience with AMD Xilinx Versal ACAP and Microchip IGLOO2, and proficiency with Vivado and Libero SoC.