FPGA Engineer (Space)

Viasat; Tempe (AZ); On-site; USD 132,500 - 209,500; Full time

Job summary

Viasat in Tempe, Arizona is seeking a Senior FPGA Engineer to design and implement high-speed signal-processing algorithms and network protocols in FPGAs. The position requires ownership of the entire design process from requirements to integration, collaborating with engineers from various fields.

The ideal candidate will have a Bachelor's Degree in Electrical Engineering and over 6 years of FPGA design experience, particularly with Xilinx Vivado. Additional skills in digital signal processing and good communication abilities are essential.

Qualifications

• 6+ years FPGA design experience, including Xilinx Vivado.
• Strong knowledge of System Verilog and/or VHDL.
• Experience with RTL design for signal processing blocks.

Responsibilities

• Own the architecture, design, and implementation of FPGA systems.
• Develop RTL in Verilog, SystemVerilog, or VHDL.
• Collaborate with team members on digital signal processing algorithms.

Skills

FPGA design experience

System Verilog

VHDL

Digital logic understanding

Signal processing experience

Lab equipment operation

Communication skills

Education

Bachelor Degree in Electrical Engineering or related field

Tools

Xilinx Vivado

Programmable Logic EDA tools

Logic analyzers

DMM

Spectrum analyzers

Job description

What you'll do

As a senior FPGA Engineer on the Space Infrastructure team, you will design, implement, and deliver high speed signal-processing algorithms, cryptography, and/or network protocols in FPGAs. You will be responsible for the full design phase starting from the requirements phase to documentation, block diagrams, implementation of source code, simulation, place and route, testing in hardware, and integration. You will collaborate with other engineers from different fields and must be capable of working in both a small team setting and a larger team setting. You will be able to use your engineering experience to support the next generation of advanced communications products and systems.

The day-to-day

• Own the architecture, design, and implementation of FPGA based digital systems
• Develop RTL in Verilog, SystemVerilog, or VHDL for control, data processing, and communication functions
• Integrate and deploy designs on FPGA and FPGA SoC platforms
• Collaborate with team members to jointly develop high-speed digital signal processing and waveform processing algorithms supporting satellite communications applications
• Develop timing constraints, analyze timing results, and implement design changes required to close timing
• Support bring up, integration, and debug in the lab using logic analyzers, scopes, and other instrumentation
• Participate and lead system level trade studies, FPGA utilization, design, and code reviews
• Maintain and control FPGA code revision history
• Create clear documentation and support test, validation, and production efforts
• Contribute to improving FPGA design standards, workflows, and development practices
• Works autonomously with little instruction to solve well-defined problems

What you'll need

• Bachelor Degree in Electrical Engineering, Computer Engineering or a related field
• 6+ years FPGA design experience, including Xilinx Vivado
• Strong knowledge of System Verilog and/or VHDL
• Foundational knowledge of digital logic and timing considerations
• Experience with RTL design for various signal processing blocks, including but not limited to equalizers, correlators, filters, FEC encoders and decoders
• Experience with Programmable Logic EDA tools, such as AMD/Xilinx ISE/Vivado, Intel/Altera Quartus, Siemens/Mentor Graphics, Synopsys Synplify
• Proven track record to design and implement FPGA modules with simulation and testbench development
• Experience designing and coding for re-use, maintainability and scalability
• Experienced in the use of lab equipment including logic analyzers, DMM, spectrum analyzers
• Ability to read schematics and work closely with hardware design teams
• Good oral and written communications skills
• US citizenship
• Ability to travel up to 10%

What will help you on the job

• MSEE degree preferred
• Familiarity with TCL, Perl, Python or another scripting language
• Experience with high-speed interfaces like SERDES, DDR2/3/4, LVDS
• System Verilog design verification techniques, UVM, or other sophisticated verification methodologies
• RTL optimization
• Experience and familiarity with Linux-based development environments
• Experience with GitHub
• Experience with Matlab
• Familiarity with CI/CD practices
• Familiarity with AI Agents (e.g. Copilot, Claude, Cursor, etc.)
• Strong troubleshooting skills
• Understanding and knowledge of Satellite communication waveforms and standards

Salary range

$132,500.00 - $209,500.00 / annually. For specific work locations within San Jose, the San Francisco Bay area and New York City metropolitan area, the base pay range for this role is $164,500.00- $246,500.00/ annually.

EEO Statement

Viasat is proud to be an equal opportunity employer, seeking to create a welcoming and diverse environment. All qualified applicants will receive consideration for employment without regard to race, color, religion, gender, gender identity or expression, sexual orientation, national origin, ancestry, physical or mental disability, medical condition, marital status, genetics, age, or veteran status or any other applicable legally protected status or characteristic. If you would like to request an accommodation on the basis of disability for completing this online application, please click here.