FPGA & ECC Design Intern – Onsite, 6 Months

Socket.dev; San Jose (CA); On-site; USD 48,000 - 62,000; Full time

Job summary

SK Hynix Memory Solution seeks a motivated intern to contribute to Start-of-Art ECC IPs. You will work on FPGA systems, collect performance data, and manage design data in Git while coding RTL in Verilog/SystemVerilog. You will run Synopsys VCS simulations and debug environments, collaborating closely with designers and verification engineers.

The internship lasts 6 months, 40 hours per week, onsite in San Jose, starting September 2026 or October 2026. Immediate availability is preferred.

Qualifications

• BS/MS degree (completed or in progress) in Electrical Engineering, Computer Engineering, or related field.
• Must have proficiency in Verilog, SystemVerilog programming language.
• Lab skills on Windows software and hardware, and FPGA system.
• Must be able to communicate with designers and verification engineers.
• Must be available to work 40 hours per week, Monday – Friday.

Responsibilities

• Perform work on running FPGA systems and collect data for performance.
• Manage design data using Git.
• Code RTL logic with Verilog syntax.
• Run simulations using Synopsys VCS.
• Debug simulation environments and resolve issues.
• Collaborate with designers and verification engineers to find correct solutions.

Skills

Verilog

SystemVerilog

FPGA

Communication

Python

Education

BS/MS in Electrical Engineering or related field

Tools

Git

Synopsys VCS

Job description

SK Hynix Memory Solution seeks a motivated intern to contribute to Start-of-Art ECC IPs. You will work on FPGA systems, collect performance data, and manage design data in Git while coding RTL in Verilog/SystemVerilog. You will run Synopsys VCS simulations and debug environments, collaborating closely with designers and verification engineers.

The internship lasts 6 months, 40 hours per week, onsite in San Jose, starting September 2026 or October 2026. Immediate availability is preferred.