Design Verification Engineer Intern - Memory Tech San Jose

Socket.dev; San Jose (CA); On-site; USD 48,000 - 62,000; Full time

Job summary

SK Hynix Memory Solution in San Jose is offering a 6-month internship for Electrical Engineering students focused on digital IC design and verification. You will study the SOC TOP microarchitecture, modify test benches, and create tests under supervision.

The role requires a BS/MS in EE, SystemVerilog/UVM, C/Assembly, and Python/Perl scripting. Experience with Perforce and Confluence is valued; start date is immediate. 40 hours per week.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering (BSEE/MSEE) or related field.
• Digital IC Design & Verification experiences.
• Windows and Linux environments.
• Python or Perl scripting experience.
• SystemVerilog, UVM, C/Assembly coding proficiency.
• Perforce and Confluence familiarity.
• UCIe, CPU architecture, NAND protocols familiarity is a plus.

Responsibilities

• Study the microarchitecture of the Design (SOC TOP) and list the Verification Requirements for testing.
• Modify the Test Bench for the SOC TOP level testing.
• Create/Modify Tests Cases to test the functionalities of the SOC.
• Debug and file bug reports to Designer.
• Testing to meet the Coverage criteria (Functional, Toggle).

Skills

SystemVerilog/UVM

C/Assembly coding

Python scripting

Digital IC design

Windows & Linux

UCIe / CPU architecture knowledge

Education

Bachelor's or Master's in Electrical Engineering (BSEE/MSEE)

Tools

Perforce

Confluence

Job description

SK Hynix Memory Solution in San Jose is offering a 6-month internship for Electrical Engineering students focused on digital IC design and verification. You will study the SOC TOP microarchitecture, modify test benches, and create tests under supervision.

The role requires a BS/MS in EE, SystemVerilog/UVM, C/Assembly, and Python/Perl scripting. Experience with Perforce and Confluence is valued; start date is immediate. 40 hours per week.