HBM SoC RTL Design Intern — Build Next-Gen Memory

Micron Technology, Inc; Folsom (CA); On-site; USD 52,000 - 69,000; Full time

Job summary

Micron Technology, Inc. is seeking a SoC Design Engineer Intern to join the Heterogeneous Integration Group (HIG). You will design RTL for SoC blocks, integrate IP, and collaborate with architecture, verification, and firmware teams to deliver robust, high-performance HB M logic.

The internship lasts six months and targets students pursuing a BS or MS in EE/CE who cannot graduate before December 2027. You will assist with pre-silicon validation, post-silicon bring-up, and design documentation.

Qualifications

• Pursuing a Bachelor's or Master's in EE/CE or related field; cannot graduate before December 2027; 6-month internship.

Responsibilities

• Design RTL for SoC-level blocks and subsystems used in HBM logic die.

Skills

SystemVerilog/Verilog

RTL-to-GDS flow

EDA tools (Cadence)

EDA tools (Synopsys)

EDA tools (Siemens)

Python/TCL/Perl scripting

Education

Bachelor’s or Master’s in Electrical/Computer Engineering or related

Tools

Cadence

Synopsys

Siemens

Job description

Micron Technology, Inc. is seeking a SoC Design Engineer Intern to join the Heterogeneous Integration Group (HIG). You will design RTL for SoC blocks, integrate IP, and collaborate with architecture, verification, and firmware teams to deliver robust, high-performance HB M logic.

The internship lasts six months and targets students pursuing a BS or MS in EE/CE who cannot graduate before December 2027. You will assist with pre-silicon validation, post-silicon bring-up, and design documentation.