ECC Design Intern - FPGA/Verilog (San Jose, Onsite)

SK hynix memory solutions; San Jose (CA); On-site; USD 48,000 - 62,000; Full time

Job summary

SK Hynix Memory Solution seeks a motivated intern to contribute to Start-of-Art ECC IPs in the ESSD area. The role focuses on FPGA system work, data collection, and RTL coding in Verilog/SystemVerilog under supervision. It requires strong lab skills and reliable communication with design and verification teams.

The internship is 6 months, onsite at San Jose, with a 40-hour workweek. Start date is immediate (Sept/Oct 2026). Compensation ranges from $35 to $45 per hour.

Qualifications

• Proficiency in Verilog/SystemVerilog programming languages.
• Lab skills on Windows software/hardware and FPGA systems.
• Must be available to work 40 hours per week, Monday–Friday.

Responsibilities

• Work on running FPGA systems and collect data for performance.
• Code RTL logic with Verilog syntax.
• Run simulations using Synopsys VCS.
• Debug simulation environments and resolve compilation/simulation issues.
• Collaborate with designers and verification engineers to find correct solutions.

Skills

Verilog

SystemVerilog

Education

EE/CE degree

Tools

Synopsys VCS

Job description

SK Hynix Memory Solution seeks a motivated intern to contribute to Start-of-Art ECC IPs in the ESSD area. The role focuses on FPGA system work, data collection, and RTL coding in Verilog/SystemVerilog under supervision. It requires strong lab skills and reliable communication with design and verification teams.

The internship is 6 months, onsite at San Jose, with a 40-hour workweek. Start date is immediate (Sept/Oct 2026). Compensation ranges from $35 to $45 per hour.