FPGA Design Engineer II – Onsite DoD-Clearance Eligible

globalhr; Tucson (AZ); On-site; USD 69,000 - 131,000; Full time

Benefits offered by this job

Relocation Eligibility

Job summary

RTX is seeking an Electrical Engineer II in the Effector Digital Products Department in Tucson, AZ, onsite. You will develop FPGA designs for major vendors using VHDL/Verilog and support RF/EO DSP, data links, and embedded processing.

Security clearance (Secret) is required to start, and eligibility for an interim clearance is noted. The role collaborates with circuit card and systems teams, with documentation and configuration management across the full design lifecycle.

Qualifications

• Master's degree in Electrical Engineering or related STEM field obtained by start date.
• Demonstrated experience with digital design and VHDL or Verilog coding.
• Familiarity with Xilinx, Altera or Microsemi/Microchip FPGAs.

Responsibilities

• Configure logic design work with circuit card designers and systems engineers to develop requirements, select parts, architect the device, perform code development, simulation and place and route.
• Designs are verified against requirements using directed test and constrained random methodologies.
• Design support from requirements definition through integration and test, and production.
• Designs are documented and configuration managed throughout the design process.

Skills

Digital design

VHDL/Verilog coding

FPGAs

Education

Master's degree in Electrical Engineering

Tools

Xilinx FPGA tools

Altera FPGA tools

Microchip/Microsemi FPGA tools

Job description

RTX is seeking an Electrical Engineer II in the Effector Digital Products Department in Tucson, AZ, onsite. You will develop FPGA designs for major vendors using VHDL/Verilog and support RF/EO DSP, data links, and embedded processing.

Security clearance (Secret) is required to start, and eligibility for an interim clearance is noted. The role collaborates with circuit card and systems teams, with documentation and configuration management across the full design lifecycle.