FPGA Design Engineer — Early-Career, Secret Clearance

Northrop Grumman; Chandler (AZ); On-site; USD 87,200 - 130,800; Full time

Benefits offered by this job

Health insurance

Paid time off

Discretionary bonus

Job summary

Northrop Grumman Space Systems in Chandler, AZ is seeking an FPGA Digital Engineer to support the EO Group inside Launch Vehicles. This early-career role focuses on learning, developing foundational skills, and contributing to FPGA design, verification, and integration under guidance.

Responsibilities include test bench development, HDL module integration, and collaboration with hardware, algorithms, and software teams.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related discipline; 2 years of relevant experience or a Master's degree.
• Ability to obtain a DoD Secret clearance at time of application.
• Internship/co-op/academic project with FPGAs, SoCs, or digital hardware (VHDL/Verilog).
• Exposure to AMD Xilinx FPGAs/SoCs (academic/project acceptable).
• Experience with design constraints (timing, power, I/O) and tools such as Vivado.

Responsibilities

• Assist senior FPGA engineers and multidisciplinary teams to resolve design and integration challenges.
• Develop and execute test benches to verify FPGA designs against functional and timing requirements.
• Support generation, verification, and integration of IO and image processing HDL modules.
• Prepare and maintain design documentation including schematics and verification reports.
• Support configuration management of FPGA bitstream builds as directed.
• Contribute to compliance with internal design standards throughout the lifecycle.

Skills

FPGA design

HDL (VHDL/Verilog)

Vivado

Digital hardware

Testing/verification

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

Tools

Vivado IDE

Questa/ModelSim

Oscilloscopes

Job description

Northrop Grumman Space Systems in Chandler, AZ is seeking an FPGA Digital Engineer to support the EO Group inside Launch Vehicles. This early-career role focuses on learning, developing foundational skills, and contributing to FPGA design, verification, and integration under guidance.

Responsibilities include test bench development, HDL module integration, and collaboration with hardware, algorithms, and software teams.