Principal FPGA Engineer — Secret Clearance, Relocation

Northrop Grumman; Chandler (AZ); On-site; USD 108,200 - 162,400; Full time

Benefits offered by this job

Relocation assistance

Discretionary bonus

Long-term incentives

Job summary

Northrop Grumman in Chandler, AZ, seeks a Principal FPGA Digital Engineer to support the EO Group within Launch Vehicles. You will design and validate FPGA architectures, develop test benches, and ensure hardware integration across teams.

The role requires a strong FPGA/SoC background, VHDL/Verilog experience, and the ability to work in a fast-paced, collaborative environment. DoD Secret clearance is required or achievable.

Qualifications

• Bachelor’s degree in Electrical or Computer Engineering or related field with 5+ years of experience; or Master’s with 3+ years; or PhD with 1+ year.
• Ability to obtain DoD Secret clearance at application time.
• Strong FPGA/SoC background with VHDL/Verilog.
• Experience with AMD Xilinx FPGAs/SoCs and timing analysis in Vivado.
• Knowledge of MOSA interfaces and verification methodologies.

Responsibilities

• Collaborate with multidisciplinary teams to resolve design and integration challenges.
• Develop and run advanced test benches to verify functional and timing requirements.
• Generate, verify, and integrate IO and image processing HDL modules with device architecture.
• Ensure compliance with internal design standards throughout development lifecycle.
• Manage multiple FPGA bitstream configurations for varied use cases.
• Prepare design documentation, simulations, and verification reports.
• Stay updated on evolving FPGA technologies and methodologies.

Skills

FPGA/SoC design

VHDL/Verilog

OSVVM/UVM

Questa/ModelSim

Education

Bachelor's degree in Electrical/Computer Engineering

Master's degree

PhD

Tools

Vivado IDE

Vitis Unified IDE

Questa/ModelSim

Job description

Northrop Grumman in Chandler, AZ, seeks a Principal FPGA Digital Engineer to support the EO Group within Launch Vehicles. You will design and validate FPGA architectures, develop test benches, and ensure hardware integration across teams.

The role requires a strong FPGA/SoC background, VHDL/Verilog experience, and the ability to work in a fast-paced, collaborative environment. DoD Secret clearance is required or achievable.