FPGA Design Engineer: Defense Systems

Actalent

Cedar Rapids (IA)

Presencial

USD 76.000 - 110.000

Jornada completa

hace 30 horas
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Ventajas ofrecidas por este puesto de trabajo

Medical, dental & vision
401(k) plan
PTO / Paid time off

Descripción de la vacante

Actalent is seeking an FPGA Design Engineer to join our defense-focused team in a fully onsite Cedar Rapids environment. You will design and implement FPGA-based digital logic for high‑performance, real‑time systems and own the complete design lifecycle from requirements through verification.

You will use VHDL and work with Xilinx/Intel/Altera toolchains, collaborating with RF, systems, hardware, and firmware engineers to ensure robust integration and top‑tier performance.

Formación

  • Several years of FPGA experience across design lifecycle.
  • Strong VHDL coding and verification skills.
  • Experience with Xilinx, Intel or Altera toolchains.

Responsabilidades

  • Design, develop, and implement FPGA-based digital logic for defense and communications systems.
  • Write, optimize, and maintain VHDL for high-performance, real-time apps.
  • Own the full FPGA design lifecycle from requirements to verification and support.
  • Collaborate with RF, systems, hardware, and firmware engineers for integration.
  • Assist in lab testing, debugging, and troubleshooting of FPGA designs.

Conocimientos

FPGA design lifecycle
VHDL
FPGA toolchains
Clear communication

Educación

Bachelor's degree in Electrical Engineering or Computer Engineering

Herramientas

Xilinx toolchain
Intel/Altera toolchains

Descripción del empleo

Actalent is seeking an FPGA Design Engineer to join our defense-focused team in a fully onsite Cedar Rapids environment. You will design and implement FPGA-based digital logic for high‑performance, real‑time systems and own the complete design lifecycle from requirements through verification.

You will use VHDL and work with Xilinx/Intel/Altera toolchains, collaborating with RF, systems, hardware, and firmware engineers to ensure robust integration and top‑tier performance.

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