FPGA Design & Analysis Engineer (Versal) – Secret

Adecco Group; El Segundo (CA); Presencial; USD 131.000 - 164.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Direct deposit

401(k)

DailyPay

Short-term disability insurance

Career counseling services

Descripción de la vacante

PDS Defense, Inc. in El Segundo, CA is seeking an Elect Design and Analy Engr 5 to lead FPGA/ASIC design initiatives. The role requires hands-on development of FPGA top-level designs, integration of IP cores, and ensuring timing closure.

The contractor will work on Versal/UltraScale devices, perform synthesis and P&R, and collaborate with system engineering for hardware/software integration. On-site work is required and security clearance is mandatory.

Formación

• 5+ years of FPGA/ASIC design experience.
• Strong Xilinx/AMD Vivado experience.
• Verilog/SystemVerilog HDL proficiency.
• Active U.S. security clearance.

Responsabilidades

• Inherit FPGA top-level design and add new functional blocks and interfaces, integrating third-party and in-house IP cores.
• Update constraint files, perform synthesis, simulation, and Place & Route to ensure timing closure and design integrity.
• Program FPGA devices, primarily from the Xilinx Versal, UltraScale, and UltraScale+ families.

Conocimientos

FPGA/ASIC design

Xilinx/AMD Vivado

Versal devices

Verilog/SystemVerilog

FPGA implementation

Security clearance

Herramientas

Xilinx Vivado

Descripción del empleo

PDS Defense, Inc. in El Segundo, CA is seeking an Elect Design and Analy Engr 5 to lead FPGA/ASIC design initiatives. The role requires hands-on development of FPGA top-level designs, integration of IP cores, and ensuring timing closure.

The contractor will work on Versal/UltraScale devices, perform synthesis and P&R, and collaborate with system engineering for hardware/software integration. On-site work is required and security clearance is mandatory.